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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-07-25 21:27:21 -0300
committerFernando Sahmkow <fsahmkow27@gmail.com>2021-11-16 22:11:28 +0100
commit95761cc6a70987b2625d68c4d9da4e2622f57808 (patch)
tree6bb64646fe8a4bc2741d260526be61b8f954dce2 /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
parent43aa695a0415821e42fabf78a8a624edaadebab7 (diff)
shader: Add integer division opcodes
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 3501d74953..50277eec37 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -72,6 +72,14 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
return ctx.OpIMul(ctx.U32[1], a, b);
}
+Id EmitSDiv32(EmitContext& ctx, Id a, Id b) {
+ return ctx.OpSDiv(ctx.U32[1], a, b);
+}
+
+Id EmitUDiv32(EmitContext& ctx, Id a, Id b) {
+ return ctx.OpUDiv(ctx.U32[1], a, b);
+}
+
Id EmitINeg32(EmitContext& ctx, Id value) {
return ctx.OpSNegate(ctx.U32[1], value);
}