diff options
| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-02-22 02:45:50 -0300 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-22 21:51:22 -0400 |
| commit | 18a766b3622baa40596490dbd4912f94e9980a76 (patch) | |
| tree | de34dbbbd81f6f980308b165a812445b224bd8fb /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |
| parent | 274897dfd59b4d08029ab7e93be4f84654abcdc8 (diff) | |
shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp index 4c0b5990dc..329dcb351d 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp @@ -58,12 +58,12 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b) { return ctx.OpIMul(ctx.U32[1], a, b); } -void EmitINeg32(EmitContext&) { - throw NotImplementedException("SPIR-V Instruction"); +Id EmitINeg32(EmitContext& ctx, Id value) { + return ctx.OpSNegate(ctx.U32[1], value); } -void EmitIAbs32(EmitContext&) { - throw NotImplementedException("SPIR-V Instruction"); +Id EmitIAbs32(EmitContext& ctx, Id value) { + return ctx.OpSAbs(ctx.U32[1], value); } Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) { |