From 18a766b3622baa40596490dbd4912f94e9980a76 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Mon, 22 Feb 2021 02:45:50 -0300
Subject: shader: Fix MOV(reg), add SHL variants and emit neg and abs
instructions
---
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
(limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 4c0b5990dc..329dcb351d 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -58,12 +58,12 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
return ctx.OpIMul(ctx.U32[1], a, b);
}
-void EmitINeg32(EmitContext&) {
- throw NotImplementedException("SPIR-V Instruction");
+Id EmitINeg32(EmitContext& ctx, Id value) {
+ return ctx.OpSNegate(ctx.U32[1], value);
}
-void EmitIAbs32(EmitContext&) {
- throw NotImplementedException("SPIR-V Instruction");
+Id EmitIAbs32(EmitContext& ctx, Id value) {
+ return ctx.OpSAbs(ctx.U32[1], value);
}
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
--
cgit v1.2.3-70-g09d2