diff options
| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-05-10 01:33:24 -0300 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-22 21:51:31 -0400 |
| commit | 8eb72ff0dc3eb428c28b578ffb3912c1bd1c42dd (patch) | |
| tree | 7101d69f5241ee8a4ea3c7a03bbc5aee89de3f39 /src/shader_recompiler/backend/glasm/emit_glasm.cpp | |
| parent | 80813b1d144a7f0f11047e7348620b720def93a9 (diff) | |
glasm: Fix moving U64 immediates to registers in GLASM
Diffstat (limited to 'src/shader_recompiler/backend/glasm/emit_glasm.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glasm/emit_glasm.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm.cpp b/src/shader_recompiler/backend/glasm/emit_glasm.cpp index e6e065e7f4..8e5d575a9a 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm.cpp @@ -43,7 +43,8 @@ struct RegWrapper { RegWrapper(EmitContext& ctx, Value value) : reg_alloc{ctx.reg_alloc}, allocated{value.type != Type::Register} { if (allocated) { - reg = value.type == Type::F64 ? reg_alloc.AllocLongReg() : reg_alloc.AllocReg(); + const bool is_long{value.type == Type::F64 || value.type == Type::U64}; + reg = is_long ? reg_alloc.AllocLongReg() : reg_alloc.AllocReg(); } else { reg = Register{value}; } |