1 files changed, 8 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 8aaa0e3811..406df1b78a 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -70,12 +70,12 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
     return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
 }
 
-void EmitShiftRightLogical32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
 }
 
-void EmitShiftRightArithmetic32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
 }
 
 Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
@@ -102,6 +102,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
     return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
 }
 
+Id EmitBitReverse32(EmitContext& ctx, Id value) {
+    return ctx.OpBitReverse(ctx.U32[1], value);
+}
+
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
     return ctx.OpSLessThan(ctx.U1, lhs, rhs);
 }