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authorSubv <subv2112@gmail.com>2018-06-04 22:56:28 -0500
committerSubv <subv2112@gmail.com>2018-06-04 22:56:28 -0500
commite7dfcdde74e0dfdb3c8da097201d90cbc48c7ff9 (patch)
treec53ffcd6a965b7483ec5013c505a963071cf7437 /src
parent8c99dd055c5727b7e4af2f20b415a1de28348208 (diff)
GPU: Corrected the branch targets for the shader bra instruction.
Diffstat (limited to 'src')
-rw-r--r--src/video_core/engines/shader_bytecode.h9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 8d4ea34013..edb4914646 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -328,15 +328,16 @@ union Instruction {
} texs;
union {
- BitField<20, 5, u64> target;
+ BitField<20, 24, u64> target;
BitField<5, 1, u64> constant_buffer;
s32 GetBranchTarget() const {
// Sign extend the branch target offset
- u32 mask = 1U << (5 - 1);
+ u32 mask = 1U << (24 - 1);
u32 value = static_cast<u32>(target);
- // The branch offset is relative to the next instruction, so add 1 to it.
- return static_cast<s32>((value ^ mask) - mask) + 1;
+ // The branch offset is relative to the next instruction and is stored in bytes, so
+ // divide it by the size of an instruction and add 1 to it.
+ return static_cast<s32>((value ^ mask) - mask) / sizeof(Instruction) + 1;
}
} bra;