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| author | bunnei <bunneidev@gmail.com> | 2018-03-19 10:33:21 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-03-19 10:33:21 -0400 |
| commit | b2d7c92caee6f916ac9b3aa3476a5ceafc8e6e0f (patch) | |
| tree | 07a410fab9206504f24b779b6631efc41e485142 /src | |
| parent | 23a0d2d7b77fa619edc7d69d0162bd3071b67b4b (diff) | |
| parent | dcae0c9a4fb950784db36b372c21aef718551eb5 (diff) | |
Merge pull request #251 from Subv/tic_tsc
GPU: Added TIC and TSC registers to the Maxwell3D register structure.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index 5d9b0043b7..096679162e 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -62,7 +62,34 @@ public: union { struct { - INSERT_PADDING_WORDS(0x582); + INSERT_PADDING_WORDS(0x557); + + struct { + u32 tsc_address_high; + u32 tsc_address_low; + u32 tsc_limit; + + GPUVAddr TSCAddress() const { + return static_cast<GPUVAddr>( + (static_cast<GPUVAddr>(tsc_address_high) << 32) | tsc_address_low); + } + } tsc; + + INSERT_PADDING_WORDS(0x3); + + struct { + u32 tic_address_high; + u32 tic_address_low; + u32 tic_limit; + + GPUVAddr TICAddress() const { + return static_cast<GPUVAddr>( + (static_cast<GPUVAddr>(tic_address_high) << 32) | tic_address_low); + } + } tic; + + INSERT_PADDING_WORDS(0x22); + struct { u32 code_address_high; u32 code_address_low; @@ -264,6 +291,8 @@ private: static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \ "Field " #field_name " has invalid position") +ASSERT_REG_POSITION(tsc, 0x557); +ASSERT_REG_POSITION(tic, 0x55D); ASSERT_REG_POSITION(code_address, 0x582); ASSERT_REG_POSITION(draw, 0x585); ASSERT_REG_POSITION(query, 0x6C0); |