diff options
| author | Mathew Maidment <mathew1800@gmail.com> | 2016-04-09 15:32:42 -0400 |
|---|---|---|
| committer | Mathew Maidment <mathew1800@gmail.com> | 2016-04-09 15:32:42 -0400 |
| commit | 0b7efc2be203dc0039f67197654b522e2270a61a (patch) | |
| tree | df930e7a81b20a4d305e625719991a625a072772 /src | |
| parent | 069e040500302afff0f4dcadd0657f6afec1c193 (diff) | |
| parent | 2efc1c93485bb668361447161e55d04257ae3fda (diff) | |
Merge pull request #1653 from mailwl/blx-lr
Fix BLX LR opcode interpretation
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index a6faf42b94..647784208d 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -4080,11 +4080,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { unsigned int inst = inst_cream->inst; if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { + const u32 jump_address = cpu->Reg[inst_cream->val.Rm]; cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); if(cpu->TFlag) cpu->Reg[14] |= 0x1; - cpu->Reg[15] = cpu->Reg[inst_cream->val.Rm] & 0xfffffffe; - cpu->TFlag = cpu->Reg[inst_cream->val.Rm] & 0x1; + cpu->Reg[15] = jump_address & 0xfffffffe; + cpu->TFlag = jump_address & 0x1; } else { cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); cpu->TFlag = 0x1; |