diff options
| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-02-22 22:59:16 -0300 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-22 21:51:22 -0400 |
| commit | e44752ddc8804961eb84f8c225bb36d5b4c77bc1 (patch) | |
| tree | 84df0e38680470a0ee8c2230625193c4156ddea6 /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |
| parent | 18a766b3622baa40596490dbd4912f94e9980a76 (diff) | |
shader: FMUL, select, RRO, and MUFU fixes
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp index 165d475b92..a5a0e1a9b2 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp @@ -48,11 +48,11 @@ IR::U32 TranslatorVisitor::GetReg39(u64 insn) { return X(reg.index); } -IR::F32 TranslatorVisitor::GetRegFloat20(u64 insn) { +IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) { return ir.BitCast<IR::F32>(GetReg20(insn)); } -IR::F32 TranslatorVisitor::GetRegFloat39(u64 insn) { +IR::F32 TranslatorVisitor::GetFloatReg39(u64 insn) { return ir.BitCast<IR::F32>(GetReg39(insn)); } @@ -110,6 +110,14 @@ IR::U32 TranslatorVisitor::GetImm32(u64 insn) { return ir.Imm32(static_cast<u32>(imm.value)); } +IR::F32 TranslatorVisitor::GetFloatImm32(u64 insn) { + union { + u64 raw; + BitField<20, 32, u64> value; + } const imm{insn}; + return ir.Imm32(Common::BitCast<f32>(static_cast<u32>(imm.value))); +} + void TranslatorVisitor::SetZFlag(const IR::U1& value) { ir.SetZFlag(value); } |