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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-02-03 16:43:04 -0300
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-22 21:51:21 -0400
commitd24a16045f0f6b0b873d5e3b5bf187c1a8c4343f (patch)
tree0108a028b437bc59dfe7864f333cf4c50a46d3b5 /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
parent6c4cc0cd062fbbba5349da1108d3c23cb330ca8a (diff)
shader: Initial instruction support
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp26
1 files changed, 25 insertions, 1 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
index 7bc7ce9f29..548c7f611d 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
@@ -16,6 +16,22 @@ void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) {
ir.SetReg(dest_reg, value);
}
+IR::U32 TranslatorVisitor::GetReg20(u64 insn) {
+ union {
+ u64 raw;
+ BitField<20, 8, IR::Reg> index;
+ } const reg{insn};
+ return X(reg.index);
+}
+
+IR::U32 TranslatorVisitor::GetReg39(u64 insn) {
+ union {
+ u64 raw;
+ BitField<39, 8, IR::Reg> index;
+ } const reg{insn};
+ return X(reg.index);
+}
+
IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
union {
u64 raw;
@@ -33,7 +49,7 @@ IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
return ir.GetCbuf(binding, byte_offset);
}
-IR::U32 TranslatorVisitor::GetImm(u64 insn) {
+IR::U32 TranslatorVisitor::GetImm20(u64 insn) {
union {
u64 raw;
BitField<20, 19, u64> value;
@@ -44,6 +60,14 @@ IR::U32 TranslatorVisitor::GetImm(u64 insn) {
return ir.Imm32(value);
}
+IR::U32 TranslatorVisitor::GetImm32(u64 insn) {
+ union {
+ u64 raw;
+ BitField<20, 32, u64> value;
+ } const imm{insn};
+ return ir.Imm32(static_cast<u32>(imm.value));
+}
+
void TranslatorVisitor::SetZFlag(const IR::U1& value) {
ir.SetZFlag(value);
}