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| author | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-03-21 02:09:14 -0400 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-22 21:51:24 -0400 |
| commit | c858b8ba97d3ff79dcff0795c1184ee356f2cd1a (patch) | |
| tree | a6b0c12aebb276c8a475b206941779d8d1af371d /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |
| parent | 112b8f00f0da0e031bb62a7a7a44469d3a5518a6 (diff) | |
shader: Implement DMUL and DFMA
Also add a missing const on DADD
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp index 2d2f6f9c65..758a0230a1 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp @@ -90,6 +90,14 @@ IR::F64 TranslatorVisitor::GetDoubleReg20(u64 insn) { return D(reg.index); } +IR::F64 TranslatorVisitor::GetDoubleReg39(u64 insn) { + union { + u64 raw; + BitField<39, 8, IR::Reg> index; + } const reg{insn}; + return D(reg.index); +} + static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) { union { u64 raw; |