diff options
| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-02-17 00:59:28 -0300 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-22 21:51:22 -0400 |
| commit | 85cce78583bc2232428a8fb39e43182877c8d5ad (patch) | |
| tree | 308f4ef2d145652e08dff1da31c72c2f00dad2e1 /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |
| parent | c67d64365a712830fe140dd36e24e2efd9b8a812 (diff) | |
shader: Primitive Vulkan integration
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp index 3c9eaddd94..079e3497f2 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp @@ -24,6 +24,14 @@ void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) { X(dest_reg, ir.BitCast<IR::U32>(value)); } +IR::U32 TranslatorVisitor::GetReg8(u64 insn) { + union { + u64 raw; + BitField<8, 8, IR::Reg> index; + } const reg{insn}; + return X(reg.index); +} + IR::U32 TranslatorVisitor::GetReg20(u64 insn) { union { u64 raw; |