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| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-02-02 21:07:00 -0300 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-22 21:51:21 -0400 |
| commit | 6c4cc0cd062fbbba5349da1108d3c23cb330ca8a (patch) | |
| tree | 544291931da8a85fafcea71964c77d9278ec7f29 /src/shader_recompiler/frontend/ir/reg.h | |
| parent | 2d48a7b4d0666ad16d03a22d85712617a0849046 (diff) | |
shader: SSA and dominance
Diffstat (limited to 'src/shader_recompiler/frontend/ir/reg.h')
| -rw-r--r-- | src/shader_recompiler/frontend/ir/reg.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/shader_recompiler/frontend/ir/reg.h b/src/shader_recompiler/frontend/ir/reg.h index 316fc4be8d..771094eb9a 100644 --- a/src/shader_recompiler/frontend/ir/reg.h +++ b/src/shader_recompiler/frontend/ir/reg.h @@ -271,6 +271,9 @@ enum class Reg : u64 { }; static_assert(static_cast<int>(Reg::RZ) == 255); +constexpr size_t NUM_USER_REGS = 255; +constexpr size_t NUM_REGS = 256; + [[nodiscard]] constexpr Reg operator+(Reg reg, int num) { if (reg == Reg::RZ) { // Adding or subtracting registers from RZ yields RZ @@ -290,8 +293,12 @@ static_assert(static_cast<int>(Reg::RZ) == 255); return reg + (-num); } +[[nodiscard]] constexpr size_t RegIndex(Reg reg) noexcept { + return static_cast<size_t>(reg); +} + [[nodiscard]] constexpr bool IsAligned(Reg reg, size_t align) { - return (static_cast<size_t>(reg) / align) * align == static_cast<size_t>(reg); + return (RegIndex(reg) / align) * align == RegIndex(reg); } } // namespace Shader::IR |