1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
|
#define SimdReg32
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdReg32")]
public sealed class CpuTestSimdReg32 : CpuTest32
{
#if SimdReg32
#region "ValueSource (Opcodes)"
private static uint[] _V_Add_Sub_Long_Wide_I_()
{
return new[]
{
0xf2800000u, // VADDL.S8 Q0, D0, D0
0xf2800100u, // VADDW.S8 Q0, Q0, D0
0xf2800200u, // VSUBL.S8 Q0, D0, D0
0xf2800300u // VSUBW.S8 Q0, Q0, D0
};
}
private static uint[] _Vfma_Vfms_Vfnma_Vfnms_S_F32_()
{
return new[]
{
0xEEA00A00u, // VFMA. F32 S0, S0, S0
0xEEA00A40u, // VFMS. F32 S0, S0, S0
0xEE900A40u, // VFNMA.F32 S0, S0, S0
0xEE900A00u // VFNMS.F32 S0, S0, S0
};
}
private static uint[] _Vfma_Vfms_Vfnma_Vfnms_S_F64_()
{
return new[]
{
0xEEA00B00u, // VFMA. F64 D0, D0, D0
0xEEA00B40u, // VFMS. F64 D0, D0, D0
0xEE900B40u, // VFNMA.F64 D0, D0, D0
0xEE900B00u // VFNMS.F64 D0, D0, D0
};
}
private static uint[] _Vfma_Vfms_V_F32_()
{
return new[]
{
0xF2000C10u, // VFMA.F32 D0, D0, D0
0xF2200C10u // VFMS.F32 D0, D0, D0
};
}
private static uint[] _Vmla_Vmls_Vnmla_Vnmls_S_F32_()
{
return new[]
{
0xEE000A00u, // VMLA. F32 S0, S0, S0
0xEE000A40u, // VMLS. F32 S0, S0, S0
0xEE100A40u, // VNMLA.F32 S0, S0, S0
0xEE100A00u // VNMLS.F32 S0, S0, S0
};
}
private static uint[] _Vmla_Vmls_Vnmla_Vnmls_S_F64_()
{
return new[]
{
0xEE000B00u, // VMLA. F64 D0, D0, D0
0xEE000B40u, // VMLS. F64 D0, D0, D0
0xEE100B40u, // VNMLA.F64 D0, D0, D0
0xEE100B00u // VNMLS.F64 D0, D0, D0
};
}
private static uint[] _Vmlal_Vmlsl_V_I_()
{
return new[]
{
0xf2800800u, // VMLAL.S8 Q0, D0, D0
0xf2800a00u // VMLSL.S8 Q0, D0, D0
};
}
private static uint[] _Vp_Add_Max_Min_F_()
{
return new[]
{
0xf3000d00u, // VPADD.F32 D0, D0, D0
0xf3000f00u, // VPMAX.F32 D0, D0, D0
0xf3200f00u // VPMIN.F32 D0, D0, D0
};
}
private static uint[] _Vp_Add_I_()
{
return new[]
{
0xf2000b10u // VPADD.I8 D0, D0, D0
};
}
private static uint[] _V_Pmax_Pmin_Rhadd_I_()
{
return new[]
{
0xf2000a00u, // VPMAX .S8 D0, D0, D0
0xf2000a10u, // VPMIN .S8 D0, D0, D0
0xf2000100u, // VRHADD.S8 D0, D0, D0
};
}
private static uint[] _Vq_Add_Sub_I_()
{
return new[]
{
0xf2000050u, // VQADD.S8 Q0, Q0, Q0
0xf2000250u // VQSUB.S8 Q0, Q0, Q0
};
}
#endregion
#region "ValueSource (Types)"
private static ulong[] _8B1D_()
{
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
0x8080808080808080ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B4H2S1D_()
{
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static IEnumerable<ulong> _1S_F_()
{
yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
yield return 0x0000000080800000ul; // -Min Normal
yield return 0x00000000807FFFFFul; // -Max Subnormal
yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
yield return 0x0000000000800000ul; // +Min Normal
yield return 0x00000000007FFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
if (!NoZeros)
{
yield return 0x0000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
if (!NoInfs)
{
yield return 0x00000000FF800000ul; // -Infinity
yield return 0x000000007F800000ul; // +Infinity
}
if (!NoNaNs)
{
yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
}
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong grbg = TestContext.CurrentContext.Random.NextUInt();
ulong rnd1 = GenNormalS();
ulong rnd2 = GenSubnormalS();
yield return (grbg << 32) | rnd1;
yield return (grbg << 32) | rnd2;
}
}
private static IEnumerable<ulong> _2S_F_()
{
yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal (float.MinValue)
yield return 0x8080000080800000ul; // -Min Normal
yield return 0x807FFFFF807FFFFFul; // -Max Subnormal
yield return 0x8000000180000001ul; // -Min Subnormal (-float.Epsilon)
yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal (float.MaxValue)
yield return 0x0080000000800000ul; // +Min Normal
yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
if (!NoZeros)
{
yield return 0x8000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
if (!NoInfs)
{
yield return 0xFF800000FF800000ul; // -Infinity
yield return 0x7F8000007F800000ul; // +Infinity
}
if (!NoNaNs)
{
yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
yield return 0x7FC000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
}
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong rnd1 = GenNormalS();
ulong rnd2 = GenSubnormalS();
yield return (rnd1 << 32) | rnd1;
yield return (rnd2 << 32) | rnd2;
}
}
private static IEnumerable<ulong> _1D_F_()
{
yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
yield return 0x8010000000000000ul; // -Min Normal
yield return 0x800FFFFFFFFFFFFFul; // -Max Subnormal
yield return 0x8000000000000001ul; // -Min Subnormal (-double.Epsilon)
yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
yield return 0x0010000000000000ul; // +Min Normal
yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
if (!NoZeros)
{
yield return 0x8000000000000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
if (!NoInfs)
{
yield return 0xFFF0000000000000ul; // -Infinity
yield return 0x7FF0000000000000ul; // +Infinity
}
if (!NoNaNs)
{
yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
yield return 0x7FF8000000000000ul; // +QNaN (all zeros payload) (-double.NaN) (DefaultNaN)
yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
}
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong rnd1 = GenNormalD();
ulong rnd2 = GenSubnormalD();
yield return rnd1;
yield return rnd2;
}
}
#endregion
private const int RndCnt = 2;
private static readonly bool NoZeros = false;
private static readonly bool NoInfs = false;
private static readonly bool NoNaNs = false;
[Test, Pairwise, Description("SHA256H.32 <Qd>, <Qn>, <Qm>")]
public void Sha256h_V([Values(0xF3000C40u)] uint opcode,
[Values(0u)] uint rd,
[Values(2u)] uint rn,
[Values(4u)] uint rm,
[Values(0xAEE65C11943FB939ul)] ulong z0,
[Values(0xA89A87F110291DA3ul)] ulong z1,
[Values(0xE9F766DB7A49EA7Dul)] ulong a0,
[Values(0x3053F46B0C2F3507ul)] ulong a1,
[Values(0x6E86A473B9D4A778ul)] ulong b0,
[Values(0x7BE4F9E638156BB1ul)] ulong b1,
[Values(0x1F1DC4A98DA9C132ul)] ulong resultL,
[Values(0xDB9A2A7B47031A0Dul)] ulong resultH)
{
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
V128 v0 = MakeVectorE0E1(z0, z1);
V128 v1 = MakeVectorE0E1(a0, a1);
V128 v2 = MakeVectorE0E1(b0, b1);
ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, runUnicorn: false);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
});
// Unicorn does not yet support hash instructions in A32.
// CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SHA256H2.32 <Qd>, <Qn>, <Qm>")]
public void Sha256h2_V([Values(0xF3100C40u)] uint opcode,
[Values(0u)] uint rd,
[Values(2u)] uint rn,
[Values(4u)] uint rm,
[Values(0xAEE65C11943FB939ul)] ulong z0,
[Values(0xA89A87F110291DA3ul)] ulong z1,
[Values(0xE9F766DB7A49EA7Dul)] ulong a0,
[Values(0x3053F46B0C2F3507ul)] ulong a1,
[Values(0x6E86A473B9D4A778ul)] ulong b0,
[Values(0x7BE4F9E638156BB1ul)] ulong b1,
[Values(0x0A1177E9D9C9B611ul)] ulong resultL,
[Values(0xF5A826404928A515ul)] ulong resultH)
{
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
V128 v0 = MakeVectorE0E1(z0, z1);
V128 v1 = MakeVectorE0E1(a0, a1);
V128 v2 = MakeVectorE0E1(b0, b1);
ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, runUnicorn: false);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
});
// Unicorn does not yet support hash instructions in A32.
// CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SHA256SU1.32 <Qd>, <Qn>, <Qm>")]
public void Sha256su1_V([Values(0xF3200C40u)] uint opcode,
[Values(0u)] uint rd,
[Values(2u)] uint rn,
[Values(4u)] uint rm,
[Values(0xAEE65C11943FB939ul)] ulong z0,
[Values(0xA89A87F110291DA3ul)] ulong z1,
[Values(0xE9F766DB7A49EA7Dul)] ulong a0,
[Values(0x3053F46B0C2F3507ul)] ulong a1,
[Values(0x6E86A473B9D4A778ul)] ulong b0,
[Values(0x7BE4F9E638156BB1ul)] ulong b1,
[Values(0x9EE69CC896D7DE66ul)] ulong resultL,
[Values(0x004A147155573E54ul)] ulong resultH)
{
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
V128 v0 = MakeVectorE0E1(z0, z1);
V128 v1 = MakeVectorE0E1(a0, a1);
V128 v2 = MakeVectorE0E1(b0, b1);
ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, runUnicorn: false);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
});
// Unicorn does not yet support hash instructions in A32.
// CompareAgainstUnicorn();
}
[Explicit]
[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
public void Vadd_F32([Values(0u)] uint rd,
[Values(0u, 1u)] uint rn,
[Values(0u, 2u)] uint rm,
[ValueSource(nameof(_2S_F_))] ulong z0,
[ValueSource(nameof(_2S_F_))] ulong z1,
[ValueSource(nameof(_2S_F_))] ulong a0,
[ValueSource(nameof(_2S_F_))] ulong a1,
[ValueSource(nameof(_2S_F_))] ulong b0,
[ValueSource(nameof(_2S_F_))] ulong b1,
[Values] bool q)
{
uint opcode = 0xf2000d00u; // VADD.F32 D0, D0, D0
if (q)
{
opcode |= 1 << 6;
rm <<= 1;
rn <<= 1;
rd <<= 1;
}
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
V128 v0 = MakeVectorE0E1(z0, z1);
V128 v1 = MakeVectorE0E1(a0, a1);
V128 v2 = MakeVectorE0E1(b0, b1);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void V_Add_Sub_Long_Wide_I([ValueSource(nameof(_V_Add_Sub_Long_Wide_I_))] uint opcode,
[Range(0u, 5u)] uint rd,
[Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
[ValueSource(nameof(_8B4H2S1D_))] ulong b,
[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
[Values] bool u) // <S, U>
{
if (u)
{
opcode |= 1 << 24;
}
rd >>= 1; rd <<= 1;
rn >>= 1; rn <<= 1;
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= (size & 0x3) << 20;
V128 v0 = MakeVectorE0E1(z, ~z);
V128 v1 = MakeVectorE0E1(a, ~a);
V128 v2 = MakeVectorE0E1(b, ~b);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VCMP.f<size> Vd, Vm")]
public void Vcmp([Values(2u, 3u)] uint size,
[ValueSource(nameof(_1S_F_))] ulong a,
[ValueSource(nameof(_1S_F_))] ulong b,
[Values] bool e)
{
uint opcode = 0xeeb40840u;
uint rm = 1;
uint rd = 2;
if (size == 3)
{
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
}
else
{
opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
}
opcode |= ((size & 3) << 8);
if (e)
{
opcode |= 1 << 7;
}
V128 v1 = MakeVectorE0(a);
V128 v2 = MakeVectorE0(b);
int fpscr = (int)(TestContext.CurrentContext.Random.NextUInt(0xf) << 28);
SingleOpcode(opcode, v1: v1, v2: v2, fpscr: fpscr);
CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv);
}
[Test, Pairwise] [Explicit] // Fused.
public void Vfma_Vfms_Vfnma_Vfnms_S_F32([ValueSource(nameof(_Vfma_Vfms_Vfnma_Vfnms_S_F32_))] uint opcode,
[Values(0u, 1u, 2u, 3u)] uint rd,
[Values(0u, 1u, 2u, 3u)] uint rn,
[Values(0u, 1u, 2u, 3u)] uint rm,
[ValueSource(nameof(_1S_F_))] ulong s0,
[ValueSource(nameof(_1S_F_))] ulong s1,
[ValueSource(nameof(_1S_F_))] ulong s2,
[ValueSource(nameof(_1S_F_))] ulong s3)
{
opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11);
opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) << 15);
opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1);
V128 v0 = MakeVectorE0E1E2E3((uint)s0, (uint)s1, (uint)s2, (uint)s3);
SingleOpcode(opcode, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit] // Fused.
public void Vfma_Vfms_Vfnma_Vfnms_S_F64([ValueSource(nameof(_Vfma_Vfms_Vfnma_Vfnms_S_F64_))] uint opcode,
[Values(0u, 1u)] uint rd,
[Values(0u, 1u)] uint rn,
[Values(0u, 1u)] uint rm,
[ValueSource(nameof(_1D_F_))] ulong d0,
[ValueSource(nameof(_1D_F_))] ulong d1)
{
opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12);
opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16);
opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0);
V128 v0 = MakeVectorE0E1(d0, d1);
SingleOpcode(opcode, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit] // Fused.
public void Vfma_Vfms_V_F32([ValueSource(nameof(_Vfma_Vfms_V_F32_))] uint opcode,
[Values(0u, 1u, 2u, 3u)] uint rd,
[Values(0u, 1u, 2u, 3u)] uint rn,
[Values(0u, 1u, 2u, 3u)] uint rm,
[ValueSource(nameof(_2S_F_))] ulong d0,
[ValueSource(nameof(_2S_F_))] ulong d1,
[ValueSource(nameof(_2S_F_))] ulong d2,
[ValueSource(nameof(_2S_F_))] ulong d3,
[Values] bool q)
{
if (q)
{
opcode |= 1 << 6;
rd >>= 1; rd <<= 1;
rn >>= 1; rn <<= 1;
rm >>= 1; rm <<= 1;
}
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
V128 v0 = MakeVectorE0E1(d0, d1);
V128 v1 = MakeVectorE0E1(d2, d3);
SingleOpcode(opcode, v0: v0, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void Vmla_Vmls_Vnmla_Vnmls_S_F32([ValueSource(nameof(_Vmla_Vmls_Vnmla_Vnmls_S_F32_))] uint opcode,
[Values(0u, 1u, 2u, 3u)] uint rd,
[Values(0u, 1u, 2u, 3u)] uint rn,
[Values(0u, 1u, 2u, 3u)] uint rm,
[ValueSource(nameof(_1S_F_))] ulong s0,
[ValueSource(nameof(_1S_F_))] ulong s1,
[ValueSource(nameof(_1S_F_))] ulong s2,
[ValueSource(nameof(_1S_F_))] ulong s3)
{
opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11);
opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) << 15);
opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1);
V128 v0 = MakeVectorE0E1E2E3((uint)s0, (uint)s1, (uint)s2, (uint)s3);
SingleOpcode(opcode, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void Vmla_Vmls_Vnmla_Vnmls_S_F64([ValueSource(nameof(_Vmla_Vmls_Vnmla_Vnmls_S_F64_))] uint opcode,
[Values(0u, 1u)] uint rd,
[Values(0u, 1u)] uint rn,
[Values(0u, 1u)] uint rm,
[ValueSource(nameof(_1D_F_))] ulong d0,
[ValueSource(nameof(_1D_F_))] ulong d1)
{
opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12);
opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16);
opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0);
V128 v0 = MakeVectorE0E1(d0, d1);
SingleOpcode(opcode, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void Vmlal_Vmlsl_I([ValueSource(nameof(_Vmlal_Vmlsl_V_I_))] uint opcode,
[Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
[Values] bool u)
{
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= size << 20;
if (u)
{
opcode |= 1 << 24;
}
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VMULL.<size> <Vd>, <Vn>, <Vm>")]
public void Vmull_I([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
[Values] bool op,
[Values] bool u)
{
uint opcode = 0xf2800c00u; // VMULL.S8 Q0, D0, D0
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
if (op)
{
opcode |= 1 << 9;
size = 0;
u = false;
}
opcode |= size << 20;
if (u)
{
opcode |= 1 << 24;
}
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VMULL.<P8, P64> <Qd>, <Dn>, <Dm>")]
public void Vmull_I_P8_P64([Values(0u, 1u)] uint rd,
[Values(0u, 1u)] uint rn,
[Values(0u, 1u)] uint rm,
[ValueSource(nameof(_8B1D_))] ulong d0,
[ValueSource(nameof(_8B1D_))] ulong d1,
[Values(0u/*, 2u*/)] uint size) // <P8, P64>
{
/*if (size == 2u)
{
Assert.Ignore("Ryujinx.Tests.Unicorn.UnicornException : Invalid instruction (UC_ERR_INSN_INVALID)");
}*/
uint opcode = 0xf2800e00u; // VMULL.P8 Q0, D0, D0
rd >>= 1; rd <<= 1;
opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12);
opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16);
opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0);
opcode |= (size & 0x3) << 20;
V128 v0 = MakeVectorE0E1(d0, d1);
SingleOpcode(opcode, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, <Vn>")]
public void Vshl([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u, 3u)] uint size,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
[Values] bool q,
[Values] bool u)
{
uint opcode = 0xf2000400u; // VSHL.S8 D0, D0, D0
if (q)
{
opcode |= 1 << 6;
rm <<= 1;
rn <<= 1;
rd <<= 1;
}
if (u)
{
opcode |= 1 << 24;
}
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= size << 20;
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Explicit]
[Test, Pairwise]
public void Vp_Add_Max_Min_F([ValueSource(nameof(_Vp_Add_Max_Min_F_))] uint opcode,
[Values(0u)] uint rd,
[Range(0u, 7u)] uint rn,
[Range(0u, 7u)] uint rm,
[ValueSource(nameof(_2S_F_))] ulong z0,
[ValueSource(nameof(_2S_F_))] ulong z1,
[ValueSource(nameof(_2S_F_))] ulong a0,
[ValueSource(nameof(_2S_F_))] ulong a1,
[ValueSource(nameof(_2S_F_))] ulong b0,
[ValueSource(nameof(_2S_F_))] ulong b1)
{
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
V128 v0 = MakeVectorE0E1(z0, z1);
V128 v1 = MakeVectorE0E1(a0, a1);
V128 v2 = MakeVectorE0E1(b0, b1);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void Vp_Add_I([ValueSource(nameof(_Vp_Add_I_))] uint opcode,
[Values(0u)] uint rd,
[Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b)
{
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= size << 20;
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void V_Pmax_Pmin_Rhadd_I([ValueSource(nameof(_V_Pmax_Pmin_Rhadd_I_))] uint opcode,
[Values(0u)] uint rd,
[Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
[Values] bool u)
{
if (u)
{
opcode |= 1 << 24;
}
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= size << 20;
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void Vq_Add_Sub_I([ValueSource(nameof(_Vq_Add_Sub_I_))] uint opcode,
[Range(0u, 5u)] uint rd,
[Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
[ValueSource(nameof(_8B4H2S1D_))] ulong b,
[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
[Values] bool u) // <S, U>
{
if (u)
{
opcode |= 1 << 24;
}
rd >>= 1; rd <<= 1;
rn >>= 1; rn <<= 1;
rm >>= 1; rm <<= 1;
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= (size & 0x3) << 20;
V128 v0 = MakeVectorE0E1(z, ~z);
V128 v1 = MakeVectorE0E1(a, ~a);
V128 v2 = MakeVectorE0E1(b, ~b);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VQDMULH.<S16, S32> <Qd>, <Qn>, <Qm>")]
public void Vqdmulh_I([Range(0u, 5u)] uint rd,
[Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
[ValueSource(nameof(_8B4H2S1D_))] ulong b,
[Values(1u, 2u)] uint size) // <S16, S32>
{
rd >>= 1; rd <<= 1;
rn >>= 1; rn <<= 1;
rm >>= 1; rm <<= 1;
uint opcode = 0xf2100b40u & ~(3u << 20); // VQDMULH.S16 Q0, Q0, Q0
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= (size & 0x3) << 20;
V128 v0 = MakeVectorE0E1(z, ~z);
V128 v1 = MakeVectorE0E1(a, ~a);
V128 v2 = MakeVectorE0E1(b, ~b);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
#endif
}
}
|