src/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

namespace ARMeilleure.Decoders
{
    class OpCodeT16ShiftReg : OpCodeT16, IOpCode32AluRsReg
    {
        public int Rm { get; }
        public int Rs { get; }
        public int Rd { get; }

        public int Rn { get; }

        public ShiftType ShiftType { get; }

        public bool? SetFlags => null;

        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16ShiftReg(inst, address, opCode);

        public OpCodeT16ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
        {
            Rd = (opCode >> 0) & 7;
            Rm = (opCode >> 0) & 7;
            Rn = (opCode >> 3) & 7;
            Rs = (opCode >> 3) & 7;

            ShiftType = (ShiftType)(((opCode >> 6) & 1) | ((opCode >> 7) & 2));
        }
    }
}