1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
static partial class InstEmit
{
private enum CselOperation
{
None,
Increment,
Invert,
Negate
}
public static void Csel(ArmEmitterContext context) => EmitCsel(context, CselOperation.None);
public static void Csinc(ArmEmitterContext context) => EmitCsel(context, CselOperation.Increment);
public static void Csinv(ArmEmitterContext context) => EmitCsel(context, CselOperation.Invert);
public static void Csneg(ArmEmitterContext context) => EmitCsel(context, CselOperation.Negate);
private static void EmitCsel(ArmEmitterContext context, CselOperation cselOp)
{
OpCodeCsel op = (OpCodeCsel)context.CurrOp;
Operand n = GetIntOrZR(context, op.Rn);
Operand m = GetIntOrZR(context, op.Rm);
if (cselOp == CselOperation.Increment)
{
m = context.Add(m, Const(m.Type, 1));
}
else if (cselOp == CselOperation.Invert)
{
m = context.BitwiseNot(m);
}
else if (cselOp == CselOperation.Negate)
{
m = context.Negate(m);
}
Operand condTrue = GetCondTrue(context, op.Cond);
Operand d = context.ConditionalSelect(condTrue, n, m);
SetIntOrZR(context, op.Rd, d);
}
}
}
|
