1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
namespace ARMeilleure.Decoders
{
class OpCode32SimdSel : OpCode32SimdRegS
{
public OpCode32SimdSelMode Cc { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, false);
public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, true);
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
{
Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3);
}
}
enum OpCode32SimdSelMode : int
{
Eq = 0,
Vs,
Ge,
Gt
}
}
|
