blob: e0b14e662eea3ba753fc72328c11ffe180d36c83 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
using ARMeilleure.IntermediateRepresentation;
using System;
namespace ARMeilleure.Decoders
{
class OpCode : IOpCode
{
public ulong Address { get; }
public int RawOpCode { get; }
public int OpCodeSizeInBytes { get; protected set; } = 4;
public InstDescriptor Instruction { get; protected set; }
public RegisterSize RegisterSize { get; protected set; }
public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
public OpCode(InstDescriptor inst, ulong address, int opCode)
{
Address = address;
RawOpCode = opCode;
Instruction = inst;
RegisterSize = RegisterSize.Int64;
}
public int GetPairsCount() => GetBitsCount() / 16;
public int GetBytesCount() => GetBitsCount() / 8;
public int GetBitsCount()
{
switch (RegisterSize)
{
case RegisterSize.Int32: return 32;
case RegisterSize.Int64: return 64;
case RegisterSize.Simd64: return 64;
case RegisterSize.Simd128: return 128;
}
throw new InvalidOperationException();
}
public OperandType GetOperandType()
{
return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64;
}
}
}
|