| Age | Commit message (Expand) | Author |
|---|
| 2021-01-04 | CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian... | LDj3SNuD |
| 2020-12-17 | Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow... | LDj3SNuD |
| 2020-12-15 | CPU: Implement VFMA (Vector) (#1762) | sharmander |
| 2020-12-07 | CPU: Implement VFNMA.F32 | F.64 (#1783) | sharmander |
| 2020-12-03 | CPU: Implement VFNMS.F32/64 (#1758) | sharmander |
| 2020-08-08 | CPU: This PR fixes Fpscr, among other things. (#1433) | LDj3SNuD |
| 2020-07-19 | Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) | Valentin PONS |
| 2020-07-17 | CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390) | LDj3SNuD |
| 2020-06-24 | Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) | riperiperi |
| 2020-03-11 | Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other... | gdkchan |
| 2020-02-24 | Add most of the A32 instruction set to ARMeilleure (#897) | riperiperi |
