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AgeCommit message (Expand)Author
2022-08-25ARMeilleure: Hardware accelerate SHA256 (#3585)1.1.230merry
2022-08-25Implement some 32-bit Thumb instructions (#3614)1.1.229gdkchan
2022-08-19A few minor documentation fixes. (#3599)1.1.224Nicholas Rodine
2022-08-18Removed unused usings. (#3593)1.1.223Nicholas Rodine
2022-08-14PreAllocator: Check if instruction supports a Vex prefix in IsVexSameOperandD...1.1.215merry
2022-08-05Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)1.1.208gdkchan
2022-07-29Move partial unmap handler to the native signal handler (#3437)1.1.199riperiperi
2022-07-06Implement CPU FCVT Half <-> Double conversion variants (#3439)1.1.165gdkchan
2022-06-05Extend uses count from ushort to uint on Operand Data structure (#3374)1.1.140gdkchan
2022-05-31Refactor CPU interface to allow the implementation of other CPU emulators (#3...1.1.134gdkchan
2022-05-02Support memory aliasing (#2954)1.1.110gdkchan
2022-04-21T32: Implement load/store single (immediate) (#3186)1.1.106merry
2022-04-09Fix tail merge from block with conditional jump to multiple returns (#3267)1.1.100gdkchan
2022-03-19InstEmitMemoryEx: Barrier after write on ordered store (#3193)1.1.77merry
2022-03-11KThread: Fix GetPsr mask (#3180)1.1.65merry
2022-03-06T32: Implement Data Processing (Modified Immediate) instructions (#3178)1.1.63merry
2022-03-05A32: Fix ALU immediate instructions (#3179)1.1.60merry
2022-03-05Decoders: Fix instruction lengths for 16-bit B instructions (#3177)1.1.59merry
2022-03-04Decoder: Exit on trapping instructions, and resume execution at trapping inst...1.1.58merry
2022-03-04T32: Implement B, B.cond, BL, BLX (#3155)1.1.57merry
2022-02-22T32: Implement ALU (shifted register) instructions (#3135)1.1.53merry
2022-02-22ARMeilleure: Implement single stepping (#3133)1.1.50merry
2022-02-22A32: Fix BLX and BXWritePC (#3151)1.1.48merry
2022-02-22Collapse AsSpan().Slice(..) calls into AsSpan(..) (#3145)1.1.47Berkan Diler
2022-02-17PPTC version increment (#3139)1.1.45gdkchan
2022-02-18Enable CPU JIT cache invalidation (#2965)1.1.44gdkchan
2022-02-18Decoders: Add IOpCode32HasSetFlags (#3136)1.1.39merry
2022-02-17ARMeilleure: Thumb support (All T16 instructions) (#3105)1.1.36merry
2022-02-17Use ReadOnlySpan<byte> compiler optimization for static data (#3130)1.1.34Berkan Diler
2022-02-11InstEmitMemory32: Literal loads always have word-aligned PC (#3104)1.1.26merry
2022-02-09Add a limit on the number of uses a constant may have (#3097)1.1.23gdkchan
2022-02-08ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)1.1.21merry
2022-02-06ARMeilleure: A32: Implement SHADD8 (#3086)1.1.18merry
2022-02-06ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087)1.1.17merry
2022-01-29Fix small precision error on CPU reciprocal estimate instructions (#3061)1.1.13gdkchan
2022-01-24Fix calls passing V128 values on Linux (#3034)1.1.7gdkchan
2022-01-21Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)gdkchan
2022-01-19Implement FCVTNS (Scalar GP) (#2953)sharmander
2022-01-16Fix return type mismatch on 32-bit titles (#3000)gdkchan
2022-01-04CPU - Implement FCVTMS (Vector) (#2937)sharmander
2021-12-19Implement CSDB instruction (#2927)gdkchan
2021-12-08Remove usage of Mono.Posix.NETStandard accross all projects (#2906)Mary
2021-12-08Implement UHADD8 instruction (#2908)Piyachet Kanda
2021-12-04misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901)Mary
2021-11-28infra: Migrate to .NET 6 (#2829)Mary
2021-10-18Add an early `TailMerge` pass (#2721)FICTURE7
2021-10-08Optimize LSRA (#2563)FICTURE7
2021-10-05Add `Operand.Label` support to `Assembler` (#2680)FICTURE7
2021-09-29Replace CacheResourceWrite with more general "precise" write (#2684)riperiperi
2021-09-29Optimize `HybridAllocator` (#2637)FICTURE7