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path: root/ARMeilleure/IntermediateRepresentation/Instruction.cs
AgeCommit message (Expand)Author
2022-01-21Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)gdkchan
2021-08-17Reduce JIT GC allocations (#2515)FICTURE7
2020-09-12Relax block ordering constraints (#1535)FICTURE7
2020-08-05Improve branch operations (#1442)Ficture Seven
2020-07-30 Implement inline memory load/store exclusive and ordered (#1413)gdkchan
2020-05-13Remove CpuId IR instruction (#1227)gdkchan
2020-03-12Use a Jump Table for direct and indirect calls/jumps, removing transitions to...riperiperi
2019-08-08Add a new JIT compiler for CPU code (#693)gdkchan