Age | Commit message (Expand) | Author |
2022-12-21 | Fix CPU FCVTN instruction implementation (slow path) (#4159)1.1.487 | gdkchan |
2022-12-18 | Revert "ARMeilleure: Add initial support for AVX512(EVEX encoding) (#3663)" (...1.1.479 | gdkchan |
2022-12-18 | ARMeilleure: Add initial support for AVX512(EVEX encoding) (#3663)1.1.478 | Wunk |
2022-10-19 | Do not clear the rejit queue when overlaps count is equal to 0. (#3721)1.1.319 | LDj3SNuD |
2022-10-19 | A32: Implement VCVTT, VCVTB (#3710)1.1.315 | merry |
2022-10-19 | A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712)1.1.314 | LDj3SNuD |
2022-10-02 | ARMeilleure: Add `gfni` acceleration (#3669)1.1.286 | Wunk |
2022-09-20 | Fpsr and Fpcr freed. (#3701)1.1.279 | LDj3SNuD |
2022-09-19 | Implemented in IR the managed methods of the ShlReg region of the SoftFallbac...1.1.273 | LDj3SNuD |
2022-09-14 | A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (...1.1.272 | merry |
2022-09-13 | Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on b...1.1.269 | gdkchan |
2022-09-13 | Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)1.1.266 | gdkchan |
2022-09-11 | Implement VRINT (vector) Arm32 NEON instructions (#3691)1.1.263 | gdkchan |
2022-09-10 | T32: Add Vfp instructions (#3690)1.1.262 | merry |
2022-09-10 | Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield i...1.1.261 | gdkchan |
2022-09-09 | Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thum...1.1.256 | gdkchan |
2022-09-09 | Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPAD...1.1.255 | gdkchan |
2022-09-08 | Implemented in IR the managed methods of the Saturating region ... (#3665)1.1.252 | LDj3SNuD |
2022-08-25 | ARMeilleure: Hardware accelerate SHA256 (#3585)1.1.230 | merry |
2022-08-25 | Implement some 32-bit Thumb instructions (#3614)1.1.229 | gdkchan |
2022-08-18 | Removed unused usings. (#3593)1.1.223 | Nicholas Rodine |
2022-08-05 | Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)1.1.208 | gdkchan |
2022-07-06 | Implement CPU FCVT Half <-> Double conversion variants (#3439)1.1.165 | gdkchan |
2022-05-31 | Refactor CPU interface to allow the implementation of other CPU emulators (#3...1.1.134 | gdkchan |
2022-03-19 | InstEmitMemoryEx: Barrier after write on ordered store (#3193)1.1.77 | merry |
2022-03-05 | A32: Fix ALU immediate instructions (#3179)1.1.60 | merry |
2022-03-04 | Decoder: Exit on trapping instructions, and resume execution at trapping inst...1.1.58 | merry |
2022-03-04 | T32: Implement B, B.cond, BL, BLX (#3155)1.1.57 | merry |
2022-02-22 | T32: Implement ALU (shifted register) instructions (#3135)1.1.53 | merry |
2022-02-22 | A32: Fix BLX and BXWritePC (#3151)1.1.48 | merry |
2022-02-18 | Enable CPU JIT cache invalidation (#2965)1.1.44 | gdkchan |
2022-02-18 | Decoders: Add IOpCode32HasSetFlags (#3136)1.1.39 | merry |
2022-02-17 | ARMeilleure: Thumb support (All T16 instructions) (#3105)1.1.36 | merry |
2022-02-17 | Use ReadOnlySpan<byte> compiler optimization for static data (#3130)1.1.34 | Berkan Diler |
2022-02-11 | InstEmitMemory32: Literal loads always have word-aligned PC (#3104)1.1.26 | merry |
2022-02-08 | ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)1.1.21 | merry |
2022-02-06 | ARMeilleure: A32: Implement SHADD8 (#3086)1.1.18 | merry |
2022-01-29 | Fix small precision error on CPU reciprocal estimate instructions (#3061)1.1.13 | gdkchan |
2022-01-21 | Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) | gdkchan |
2022-01-19 | Implement FCVTNS (Scalar GP) (#2953) | sharmander |
2022-01-16 | Fix return type mismatch on 32-bit titles (#3000) | gdkchan |
2022-01-04 | CPU - Implement FCVTMS (Vector) (#2937) | sharmander |
2021-12-19 | Implement CSDB instruction (#2927) | gdkchan |
2021-12-08 | Implement UHADD8 instruction (#2908) | Piyachet Kanda |
2021-09-29 | Use normal memory store path for DC ZVA (#2693) | riperiperi |
2021-09-14 | Refactor `PtcInfo` (#2625) | FICTURE7 |
2021-08-27 | Implement MSR instruction for A32 (#2585) | Mary |
2021-08-17 | Reduce JIT GC allocations (#2515) | FICTURE7 |
2021-06-23 | Implement VORN (register) Arm32 instruction (#2396) | gdkchan |
2021-05-29 | Add multi-level function table (#2228) | FICTURE7 |