Age | Commit message (Expand) | Author |
2022-08-18 | Removed unused usings. (#3593)1.1.223 | Nicholas Rodine |
2022-08-05 | Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)1.1.208 | gdkchan |
2022-04-21 | T32: Implement load/store single (immediate) (#3186)1.1.106 | merry |
2022-03-06 | T32: Implement Data Processing (Modified Immediate) instructions (#3178)1.1.63 | merry |
2022-03-05 | Decoders: Fix instruction lengths for 16-bit B instructions (#3177)1.1.59 | merry |
2022-03-04 | Decoder: Exit on trapping instructions, and resume execution at trapping inst...1.1.58 | merry |
2022-03-04 | T32: Implement B, B.cond, BL, BLX (#3155)1.1.57 | merry |
2022-02-22 | T32: Implement ALU (shifted register) instructions (#3135)1.1.53 | merry |
2022-02-22 | ARMeilleure: Implement single stepping (#3133)1.1.50 | merry |
2022-02-18 | Decoders: Add IOpCode32HasSetFlags (#3136)1.1.39 | merry |
2022-02-17 | ARMeilleure: Thumb support (All T16 instructions) (#3105)1.1.36 | merry |
2022-02-08 | ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)1.1.21 | merry |
2022-02-06 | ARMeilleure: A32: Implement SHADD8 (#3086)1.1.18 | merry |
2022-02-06 | ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087)1.1.17 | merry |
2022-01-19 | Implement FCVTNS (Scalar GP) (#2953) | sharmander |
2022-01-04 | CPU - Implement FCVTMS (Vector) (#2937) | sharmander |
2021-12-19 | Implement CSDB instruction (#2927) | gdkchan |
2021-12-08 | Implement UHADD8 instruction (#2908) | Piyachet Kanda |
2021-08-27 | Implement MSR instruction for A32 (#2585) | Mary |
2021-06-23 | Implement VORN (register) Arm32 instruction (#2396) | gdkchan |
2021-04-18 | Add inlined on translation call counting (#2190) | FICTURE7 |
2021-03-25 | Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139) | LDj3SNuD |
2021-02-22 | Implement VCNT instruction (#1963) | mageven |
2021-01-26 | Implement PRFM (register variant) as NOP (#1956) | mageven |
2021-01-20 | CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests... | LDj3SNuD |
2021-01-04 | CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian... | LDj3SNuD |
2020-12-17 | Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow... | LDj3SNuD |
2020-12-17 | PPTC Follow-up. (#1712) | LDj3SNuD |
2020-12-16 | CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776) | sharmander |
2020-12-15 | CPU: Implement VFMA (Vector) (#1762) | sharmander |
2020-12-07 | CPU: Implement VFNMA.F32 | F.64 (#1783) | sharmander |
2020-12-03 | CPU: Implement VFNMS.F32/64 (#1758) | sharmander |
2020-10-21 | Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626) | gdkchan |
2020-10-13 | Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths... | LDj3SNuD |
2020-09-01 | SIMD&FP load/store with scale > 4 should be undefined (#1522) | gdkchan |
2020-08-31 | CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492) | LDj3SNuD |
2020-08-13 | Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471) | LDj3SNuD |
2020-07-19 | Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) | Valentin PONS |
2020-07-17 | CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394) | LDj3SNuD |
2020-07-17 | CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390) | LDj3SNuD |
2020-07-15 | Fix Decode exception condition (#1377) | Ficture Seven |
2020-07-13 | Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) | LDj3SNuD |
2020-07-13 | Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli vari... | riperiperi |
2020-06-24 | Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) | riperiperi |
2020-06-18 | Generalize tail continues (#1298) | Ficture Seven |
2020-06-16 | Add Profiled Persistent Translation Cache. (#769) | LDj3SNuD |
2020-06-14 | VABS takes one input register, not two. (#1300) | riperiperi |
2020-05-27 | Add FMaxNmV & FMinNmV Inst.s with Test. (#1279) | LDj3SNuD |
2020-05-04 | Implement a new physical memory manager and replace DeviceMemory (#856) | gdkchan |
2020-03-24 | Add Fcvtas_S/V & Fcvtau_S/V. (#1018) | LDj3SNuD |