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| author | Ac_K <Acoustik666@gmail.com> | 2024-01-30 00:51:05 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-30 00:51:05 +0100 |
| commit | 8bf102d2cd744f56e2a4839fa0391acda3e201b8 (patch) | |
| tree | 532c11f042b0811f6cf1179a46bfdcbf56393b26 /src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | |
| parent | 2adf0318300a0f444c8051aceba1e4759fbedc6f (diff) | |
Cpu: Implement Vpadal and Vrintr instructions (#6185)1.1.1150
* Cpu: Implement Vpadal and Vrintr instructions
This PR superseed last instructions left in #2242.
Since I'm not a CPU guy I've just ported the code and nothing more.
Please be precise during review if there are some changes to be done.
It should fixes #1781
Co-Authored-By: Piyachet Kanda <piyachetk@gmail.com>
* Addresses gdkchan's feedback
* Addresses gdkchan's feedback 2
* Apply suggestions from code review
Co-authored-by: gdkchan <gab.dark.100@gmail.com>
* another fix
* Update InstEmitSimdHelper32.cs
* Correct fix
* Addresses gdkchan's feedback
* Update CpuTestSimdCvt32.cs
---------
Co-authored-by: Piyachet Kanda <piyachetk@gmail.com>
Co-authored-by: gdkchan <gab.dark.100@gmail.com>
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 9d9606bb..38e08bf8 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -908,6 +908,44 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + + [Test, Pairwise] + public void Vp_Add_Long_Accumulate([Values(0u, 2u, 4u, 8u)] uint rd, + [Values(0u, 2u, 4u, 8u)] uint rm, + [Values(0u, 1u, 2u)] uint size, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b, + [Values] bool q, + [Values] bool unsigned) + { + uint opcode = 0xF3B00600; // VPADAL.S8 D0, Q0 + + if (q) + { + opcode |= 1 << 6; + rm <<= 1; + rd <<= 1; + } + + if (unsigned) + { + opcode |= 1 << 7; + } + + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); + + opcode |= size << 18; + + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(a, z); + V128 v2 = MakeVectorE0E1(b, z); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(); + } #endif } } |