diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2023-01-29 08:37:52 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-29 08:37:52 -0300 |
| commit | a53cfdab78c382677eb826bd5bedb58b3b838796 (patch) | |
| tree | 74443a950127d61abb6ecd9f840c03886b223ce1 /Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs | |
| parent | c7f9962ddee502030e790a0bfc0f949eaf5910c7 (diff) | |
Initial Apple Hypervisor based CPU emulation (#4332)1.1.597
* Initial Apple Hypervisor based CPU emulation implementation
* Add UseHypervisor Setting
* Add basic MacOS support to Avalonia
* Fix initialization
* Fix GTK build
* Fix/silence warnings
* Change exceptions to asserts on HvAddressSpaceRange
* Replace DllImport with LibraryImport
* Fix LibraryImport
* Remove unneeded usings
* Revert outdated change
* Set DiskCacheLoadState when using hypervisor too
* Fix HvExecutionContext PC value
* Address PR feedback
* Use existing entitlements.xml file on distribution folder
---------
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Diffstat (limited to 'Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs')
| -rw-r--r-- | Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs b/Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs new file mode 100644 index 00000000..adf2dd99 --- /dev/null +++ b/Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs @@ -0,0 +1,46 @@ +using ARMeilleure.State; + +namespace Ryujinx.Cpu.AppleHv +{ + public interface IHvExecutionContext + { + ulong Pc { get; set; } + ulong ElrEl1 { get; set; } + ulong EsrEl1 { get; set; } + + long TpidrEl0 { get; set; } + long TpidrroEl0 { get; set; } + + uint Pstate { get; set; } + + uint Fpcr { get; set; } + uint Fpsr { get; set; } + + ulong GetX(int index); + void SetX(int index, ulong value); + + V128 GetV(int index); + void SetV(int index, V128 value); + + public void Load(IHvExecutionContext context) + { + Pc = context.Pc; + ElrEl1 = context.ElrEl1; + EsrEl1 = context.EsrEl1; + TpidrEl0 = context.TpidrEl0; + TpidrroEl0 = context.TpidrroEl0; + Pstate = context.Pstate; + Fpcr = context.Fpcr; + Fpsr = context.Fpsr; + + for (int i = 0; i < 32; i++) + { + SetX(i, context.GetX(i)); + SetV(i, context.GetV(i)); + } + } + + void RequestInterrupt(); + bool GetAndClearInterruptRequested(); + } +}
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