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| author | gdkchan <gab.dark.100@gmail.com> | 2019-01-24 23:59:53 -0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-24 23:59:53 -0200 |
| commit | 36b9ab0e48b6893c057a954e1ef3181b452add1c (patch) | |
| tree | 16a4ae56019b55d0cb61f1aa105481933ada733e /ChocolArm64/Decoders/OpCodeSimdFcond64.cs | |
| parent | 72157e03eb09d4fb5d6d004efc2d13d3194e8c90 (diff) | |
Add ARM32 support on the translator (#561)
* Remove ARM32 interpreter and add ARM32 support on the translator
* Nits.
* Rename Cond -> Condition
* Align code again
* Rename Data to Alu
* Enable ARM32 support and handle undefined instructions
* Use the IsThumb method to check if its a thumb opcode
* Remove another 32-bits check
Diffstat (limited to 'ChocolArm64/Decoders/OpCodeSimdFcond64.cs')
| -rw-r--r-- | ChocolArm64/Decoders/OpCodeSimdFcond64.cs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs index f805b3c1..47de231c 100644 --- a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs +++ b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs @@ -6,12 +6,12 @@ namespace ChocolArm64.Decoders { public int Nzcv { get; private set; } - public Cond Cond { get; private set; } + public Condition Cond { get; private set; } public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode) { - Nzcv = (opCode >> 0) & 0xf; - Cond = (Cond)((opCode >> 12) & 0xf); + Nzcv = (opCode >> 0) & 0xf; + Cond = (Condition)((opCode >> 12) & 0xf); } } } |