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| author | Wunk <wunkolo@gmail.com> | 2022-10-02 02:17:19 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-02 11:17:19 +0200 |
| commit | 45ce540b9b756f372840e923b73cfd7e3edd85f8 (patch) | |
| tree | 5908b97b09330f91c893c6c25a3a76519e8651de /ARMeilleure/Translation/PTC/Ptc.cs | |
| parent | 96bf7f8522e38c36d792a6ac2173497c3674e920 (diff) | |
ARMeilleure: Add `gfni` acceleration (#3669)1.1.286
* ARMeilleure: Add `GFNI` detection
This is intended for utilizing the `gf2p8affineqb` instruction
* ARMeilleure: Add `gf2p8affineqb`
Not using the VEX or EVEX-form of this instruction is intentional. There
are `GFNI`-chips that do not support AVX(so no VEX encoding) such as
Tremont(Lakefield) chips as well as Jasper Lake.
https://github.com/InstLatx64/InstLatx64/blob/13df339fe7150b114929f71b19a6b2fe72fc751e/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt#L1297-L1299
https://github.com/InstLatx64/InstLatx64/blob/13df339fe7150b114929f71b19a6b2fe72fc751e/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt#L1252-L1254
* ARMeilleure: Add `gfni` acceleration of `Rbit_V`
Passes all `Rbit_V*` unit tests on my `i9-11900k`
* ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V`
Also added a fast-path for when the shift amount is greater than the
size of the element.
* ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V`
* ARMeilleure: Increment InternalVersion
* ARMeilleure: Fix Intrinsic and Assembler Table alignment
`gf2p8affineqb` is the longest instruction name I know of. It shouldn't
get any wider than this.
* ARMeilleure: Remove SSE2+SHA requirement for GFNI
* ARMeilleure Add `X86GetGf2p8LogicalShiftLeft`
Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction.
* ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
Diffstat (limited to 'ARMeilleure/Translation/PTC/Ptc.cs')
| -rw-r--r-- | ARMeilleure/Translation/PTC/Ptc.cs | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/ARMeilleure/Translation/PTC/Ptc.cs b/ARMeilleure/Translation/PTC/Ptc.cs index f4ae411b..1515713b 100644 --- a/ARMeilleure/Translation/PTC/Ptc.cs +++ b/ARMeilleure/Translation/PTC/Ptc.cs @@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC private const string OuterHeaderMagicString = "PTCohd\0\0"; private const string InnerHeaderMagicString = "PTCihd\0\0"; - private const uint InternalVersion = 3703; //! To be incremented manually for each change to the ARMeilleure project. + private const uint InternalVersion = 3710; //! To be incremented manually for each change to the ARMeilleure project. private const string ActualDir = "0"; private const string BackupDir = "1"; @@ -951,7 +951,8 @@ namespace ARMeilleure.Translation.PTC return new FeatureInfo( (uint)HardwareCapabilities.FeatureInfo1Ecx, (uint)HardwareCapabilities.FeatureInfo1Edx, - (uint)HardwareCapabilities.FeatureInfo7Ebx); + (uint)HardwareCapabilities.FeatureInfo7Ebx, + (uint)HardwareCapabilities.FeatureInfo7Ecx); } private static byte GetMemoryManagerMode() @@ -971,7 +972,7 @@ namespace ARMeilleure.Translation.PTC return osPlatform; } - [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 54*/)] + [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 58*/)] private struct OuterHeader { public ulong Magic; @@ -1002,8 +1003,8 @@ namespace ARMeilleure.Translation.PTC } } - [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 12*/)] - private record struct FeatureInfo(uint FeatureInfo0, uint FeatureInfo1, uint FeatureInfo2); + [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 16*/)] + private record struct FeatureInfo(uint FeatureInfo0, uint FeatureInfo1, uint FeatureInfo2, uint FeatureInfo3); [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 128*/)] private struct InnerHeader |