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authormerry <git@mary.rs>2022-03-19 13:32:35 +0000
committerGitHub <noreply@github.com>2022-03-19 10:32:35 -0300
commitdf70442c46e7ee133b1fb79dc23ddd134e618085 (patch)
tree11ab8c5d2b9f8cf5e032854e99dc4212c76a93a3 /ARMeilleure/Instructions/InstEmitMemoryEx.cs
parente2ffa5a125fcbe8a25c73d8e04c08c08ef378860 (diff)
InstEmitMemoryEx: Barrier after write on ordered store (#3193)1.1.77
* InstEmitMemoryEx: Barrier after write on ordered store * increment ptc version * 32
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitMemoryEx.cs')
-rw-r--r--ARMeilleure/Instructions/InstEmitMemoryEx.cs10
1 files changed, 5 insertions, 5 deletions
diff --git a/ARMeilleure/Instructions/InstEmitMemoryEx.cs b/ARMeilleure/Instructions/InstEmitMemoryEx.cs
index 88b9d2f0..af6adfb9 100644
--- a/ARMeilleure/Instructions/InstEmitMemoryEx.cs
+++ b/ARMeilleure/Instructions/InstEmitMemoryEx.cs
@@ -130,11 +130,6 @@ namespace ARMeilleure.Instructions
bool ordered = (accType & AccessType.Ordered) != 0;
bool exclusive = (accType & AccessType.Exclusive) != 0;
- if (ordered)
- {
- EmitBarrier(context);
- }
-
Operand address = context.Copy(GetIntOrSP(context, op.Rn));
Operand t = GetIntOrZR(context, op.Rt);
@@ -163,6 +158,11 @@ namespace ARMeilleure.Instructions
{
EmitStoreExclusive(context, address, t, exclusive, op.Size, op.Rs, a32: false);
}
+
+ if (ordered)
+ {
+ EmitBarrier(context);
+ }
}
private static void EmitBarrier(ArmEmitterContext context)