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| author | merry <git@mary.rs> | 2022-02-22 22:11:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-22 19:11:28 -0300 |
| commit | 7b35ebc64a411e95e197bb36ad4b55c522c3703d (patch) | |
| tree | ce0db30b7c5f2111546cbe46121423ca7febf19f /ARMeilleure/Instructions/InstEmitHelper.cs | |
| parent | 0a24aa6af26cc55c079e265a071a42569d28d2c0 (diff) | |
T32: Implement ALU (shifted register) instructions (#3135)1.1.53
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitHelper.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitHelper.cs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ARMeilleure/Instructions/InstEmitHelper.cs b/ARMeilleure/Instructions/InstEmitHelper.cs index 433b0831..773f6bd6 100644 --- a/ARMeilleure/Instructions/InstEmitHelper.cs +++ b/ARMeilleure/Instructions/InstEmitHelper.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Instructions { public static bool IsThumb(OpCode op) { - return op is OpCodeT16; + return op is OpCodeT16 || op is OpCodeT32; } public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type) |