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author | merry <git@mary.rs> | 2022-02-22 22:11:28 +0000 |
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committer | GitHub <noreply@github.com> | 2022-02-22 19:11:28 -0300 |
commit | 7b35ebc64a411e95e197bb36ad4b55c522c3703d (patch) | |
tree | ce0db30b7c5f2111546cbe46121423ca7febf19f /ARMeilleure/Diagnostics/EventSources | |
parent | 0a24aa6af26cc55c079e265a071a42569d28d2c0 (diff) |
T32: Implement ALU (shifted register) instructions (#3135)1.1.53
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
Diffstat (limited to 'ARMeilleure/Diagnostics/EventSources')
0 files changed, 0 insertions, 0 deletions