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authormerry <git@mary.rs>2022-04-21 00:25:43 +0100
committerGitHub <noreply@github.com>2022-04-21 01:25:43 +0200
commit6a1a03566aa04d6e3e32547821aae0bc587d1128 (patch)
treec5a14a833469753ef102fc4446e1c7c95628bc63 /ARMeilleure/Decoders/OpCodeT32MemImm8.cs
parent13f5294aa3b8b179255fee1d49111896d5510800 (diff)
T32: Implement load/store single (immediate) (#3186)1.1.106
* T32: Implement load/store single (immediate) * tests * tidy formatting * address comments
Diffstat (limited to 'ARMeilleure/Decoders/OpCodeT32MemImm8.cs')
-rw-r--r--ARMeilleure/Decoders/OpCodeT32MemImm8.cs29
1 files changed, 29 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCodeT32MemImm8.cs b/ARMeilleure/Decoders/OpCodeT32MemImm8.cs
new file mode 100644
index 00000000..d8b7763c
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCodeT32MemImm8.cs
@@ -0,0 +1,29 @@
+namespace ARMeilleure.Decoders
+{
+ class OpCodeT32MemImm8 : OpCodeT32, IOpCode32Mem
+ {
+ public int Rt { get; }
+ public int Rn { get; }
+ public bool WBack { get; }
+ public bool IsLoad { get; }
+ public bool Index { get; }
+ public bool Add { get; }
+ public int Immediate { get; }
+
+ public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemImm8(inst, address, opCode);
+
+ public OpCodeT32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+ {
+ Rt = (opCode >> 12) & 0xf;
+ Rn = (opCode >> 16) & 0xf;
+
+ Index = ((opCode >> 10) & 1) != 0;
+ Add = ((opCode >> 9) & 1) != 0;
+ WBack = ((opCode >> 8) & 1) != 0;
+
+ Immediate = opCode & 0xff;
+
+ IsLoad = ((opCode >> 20) & 1) != 0;
+ }
+ }
+} \ No newline at end of file