diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2022-09-09 22:09:11 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-09 22:09:11 -0300 |
| commit | c64524a240671cb3f8609e3454576e69e5948a60 (patch) | |
| tree | b02fe220963b33b4292adf7b4a5236dae6bc0b05 /ARMeilleure/Decoders/OpCodeT32AluReg.cs | |
| parent | db45688aa8d0e63d3ffbe50351722ef32f8360f8 (diff) | |
Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)1.1.256
* Add ADD (zx imm12), NOP, MOV (register shifted), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions, fix LDRD, STRD, CBZ, CBNZ and BLX (reg)
* Bump PPTC version
Diffstat (limited to 'ARMeilleure/Decoders/OpCodeT32AluReg.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCodeT32AluReg.cs | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCodeT32AluReg.cs b/ARMeilleure/Decoders/OpCodeT32AluReg.cs new file mode 100644 index 00000000..a487f55a --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32AluReg.cs @@ -0,0 +1,14 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32AluReg : OpCodeT32Alu, IOpCode32AluReg + { + public int Rm { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluReg(inst, address, opCode); + + public OpCodeT32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rm = (opCode >> 0) & 0xf; + } + } +}
\ No newline at end of file |