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authormerry <git@mary.rs>2022-09-13 22:25:37 +0100
committerGitHub <noreply@github.com>2022-09-13 18:25:37 -0300
commite05bf90af600f5c75a13a0b4113b7fc6a641ff6a (patch)
tree87c8d482dcba254aa39221a406490d23378a3f87 /ARMeilleure/Decoders/OpCode32SimdBase.cs
parent66f16f43921bdd6d0f706d09aa37166d374dec2e (diff)
T32: Implement Asimd instructions (#3692)1.1.268
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdBase.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdBase.cs5
1 files changed, 4 insertions, 1 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdBase.cs b/ARMeilleure/Decoders/OpCode32SimdBase.cs
index 183378b9..4382fc2a 100644
--- a/ARMeilleure/Decoders/OpCode32SimdBase.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdBase.cs
@@ -47,6 +47,9 @@ namespace ARMeilleure.Decoders
throw new InvalidOperationException();
}
- public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
+ protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
+ {
+ IsThumb = isThumb;
+ }
}
}