diff options
| author | merry <git@mary.rs> | 2022-03-04 22:05:08 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-03-04 23:05:08 +0100 |
| commit | bd9ac0fdaadd233e778a872c48f7f628b5a68c93 (patch) | |
| tree | 223f2c24430fb2643f70b423f87b8f0274e36f08 /ARMeilleure/Decoders/OpCode32.cs | |
| parent | ac21abbb9d23432879b1026eb5bc48ad3d4583d8 (diff) | |
T32: Implement B, B.cond, BL, BLX (#3155)1.1.57
* Decoders: Make IsThumb a function of OpCode32
* OpCode32: Fix GetPc
* T32: Implement B, B.cond, BL, BLX
* rm usings
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32.cs | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/ARMeilleure/Decoders/OpCode32.cs b/ARMeilleure/Decoders/OpCode32.cs index 0d8ad1fd..92487c6e 100644 --- a/ARMeilleure/Decoders/OpCode32.cs +++ b/ARMeilleure/Decoders/OpCode32.cs @@ -13,11 +13,25 @@ namespace ARMeilleure.Decoders Cond = (Condition)((uint)opCode >> 28); } + public bool IsThumb() + { + return this is OpCodeT16 || this is OpCodeT32; + } + public uint GetPc() { // Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline, // the PC actually points 2 instructions ahead. - return (uint)Address + (uint)OpCodeSizeInBytes * 2; + if (IsThumb()) + { + // PC is ahead by 4 in thumb mode whether or not the current instruction + // is 16 or 32 bit. + return (uint)Address + 4u; + } + else + { + return (uint)Address + 8u; + } } } }
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