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| author | merry <git@mary.rs> | 2022-02-22 22:11:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-22 19:11:28 -0300 |
| commit | 7b35ebc64a411e95e197bb36ad4b55c522c3703d (patch) | |
| tree | ce0db30b7c5f2111546cbe46121423ca7febf19f /ARMeilleure/Decoders/Decoder.cs | |
| parent | 0a24aa6af26cc55c079e265a071a42569d28d2c0 (diff) | |
T32: Implement ALU (shifted register) instructions (#3135)1.1.53
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
Diffstat (limited to 'ARMeilleure/Decoders/Decoder.cs')
| -rw-r--r-- | ARMeilleure/Decoders/Decoder.cs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/Decoder.cs b/ARMeilleure/Decoders/Decoder.cs index e4839bf7..af3b0629 100644 --- a/ARMeilleure/Decoders/Decoder.cs +++ b/ARMeilleure/Decoders/Decoder.cs @@ -263,6 +263,11 @@ namespace ARMeilleure.Decoders // so we must consider such operations as a branch in potential aswell. if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc) { + if (opCode is OpCodeT32) + { + return opCode.Instruction.Name != InstName.Tst && opCode.Instruction.Name != InstName.Teq && + opCode.Instruction.Name != InstName.Cmp && opCode.Instruction.Name != InstName.Cmn; + } return true; } |