From be94ee88d227d0d3dbeabe9ade98bacd910c7a7e Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Fri, 5 Feb 2021 19:19:36 -0300
Subject: shader: Make typed IR
---
.../frontend/maxwell/translate/impl/impl.cpp | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
(limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
index 548c7f611d..3c9eaddd94 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
@@ -12,10 +12,18 @@ IR::U32 TranslatorVisitor::X(IR::Reg reg) {
return ir.GetReg(reg);
}
+IR::F32 TranslatorVisitor::F(IR::Reg reg) {
+ return ir.BitCast<IR::F32>(X(reg));
+}
+
void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) {
ir.SetReg(dest_reg, value);
}
+void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) {
+ X(dest_reg, ir.BitCast<IR::U32>(value));
+}
+
IR::U32 TranslatorVisitor::GetReg20(u64 insn) {
union {
u64 raw;
@@ -32,6 +40,14 @@ IR::U32 TranslatorVisitor::GetReg39(u64 insn) {
return X(reg.index);
}
+IR::F32 TranslatorVisitor::GetReg20F(u64 insn) {
+ return ir.BitCast<IR::F32>(GetReg20(insn));
+}
+
+IR::F32 TranslatorVisitor::GetReg39F(u64 insn) {
+ return ir.BitCast<IR::F32>(GetReg39(insn));
+}
+
IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
union {
u64 raw;
@@ -49,6 +65,10 @@ IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
return ir.GetCbuf(binding, byte_offset);
}
+IR::F32 TranslatorVisitor::GetCbufF(u64 insn) {
+ return ir.BitCast<IR::F32>(GetCbuf(insn));
+}
+
IR::U32 TranslatorVisitor::GetImm20(u64 insn) {
union {
u64 raw;
--
cgit v1.2.3-70-g09d2