From 274897dfd59b4d08029ab7e93be4f84654abcdc8 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Sun, 21 Feb 2021 23:42:38 -0300
Subject: spirv: Fixes and Intel specific workarounds
---
.../frontend/maxwell/translate/impl/impl.cpp | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
(limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
index be17bb0d9f..165d475b92 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
@@ -83,9 +83,12 @@ IR::U32 TranslatorVisitor::GetImm20(u64 insn) {
BitField<20, 19, u64> value;
BitField<56, 1, u64> is_negative;
} const imm{insn};
- const s32 positive_value{static_cast<s32>(imm.value)};
- const s32 value{imm.is_negative != 0 ? -positive_value : positive_value};
- return ir.Imm32(value);
+ if (imm.is_negative != 0) {
+ const s64 raw{static_cast<s64>(imm.value)};
+ return ir.Imm32(static_cast<s32>(-(1LL << 19) + raw));
+ } else {
+ return ir.Imm32(static_cast<u32>(imm.value));
+ }
}
IR::F32 TranslatorVisitor::GetFloatImm20(u64 insn) {
@@ -94,9 +97,9 @@ IR::F32 TranslatorVisitor::GetFloatImm20(u64 insn) {
BitField<20, 19, u64> value;
BitField<56, 1, u64> is_negative;
} const imm{insn};
- const f32 positive_value{Common::BitCast<f32>(static_cast<u32>(imm.value) << 12)};
- const f32 value{imm.is_negative != 0 ? -positive_value : positive_value};
- return ir.Imm32(value);
+ const u32 sign_bit{imm.is_negative != 0 ? (1ULL << 31) : 0};
+ const u32 value{static_cast<u32>(imm.value) << 12};
+ return ir.Imm32(Common::BitCast<f32>(value | sign_bit));
}
IR::U32 TranslatorVisitor::GetImm32(u64 insn) {
--
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