From cbfb7d182a4e90e4e263696d1fca35e47d3eabb4 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Sun, 14 Feb 2021 20:15:42 -0300
Subject: shader: Support SSA loops on IR
---
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
(limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 3ef4f3d787..e811a63ab3 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -73,8 +73,8 @@ Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id coun
return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
}
-void EmitSPIRV::EmitSLessThan(EmitContext&) {
- throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
+ return ctx.OpSLessThan(ctx.u1, lhs, rhs);
}
void EmitSPIRV::EmitULessThan(EmitContext&) {
@@ -93,8 +93,8 @@ void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
}
-void EmitSPIRV::EmitSGreaterThan(EmitContext&) {
- throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
+ return ctx.OpSGreaterThan(ctx.u1, lhs, rhs);
}
void EmitSPIRV::EmitUGreaterThan(EmitContext&) {
--
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