+ set(CMAKE_EXE_LINKER_FLAGS_RELEASE "/DEBUG /INCREMENTAL:NO /OPT:REF,ICF" CACHE STRING "" FORCE)

+Subproject 676254f71e0a7ef0aca8acce078d3c3dc80ccf7

+static const std::array<int, Settings::NativeInput::NUM_INPUTS> defaults = {

+ GLFW_KEY_A, GLFW_KEY_S, GLFW_KEY_Z, GLFW_KEY_X,

+ GLFW_KEY_Q, GLFW_KEY_W, GLFW_KEY_1, GLFW_KEY_2,

+ GLFW_KEY_M, GLFW_KEY_N, GLFW_KEY_B,

+ GLFW_KEY_T, GLFW_KEY_G, GLFW_KEY_F, GLFW_KEY_H,

+ GLFW_KEY_UP, GLFW_KEY_DOWN, GLFW_KEY_LEFT, GLFW_KEY_RIGHT,

+ GLFW_KEY_I, GLFW_KEY_K, GLFW_KEY_J, GLFW_KEY_L

+};

+

+ for (int i = 0; i < Settings::NativeInput::NUM_INPUTS; ++i) {

+ Settings::values.input_mappings[Settings::NativeInput::All[i]] =

+ glfw_config->GetInteger("Controls", Settings::NativeInput::Mapping[i], defaults[i]);

+ }

+ for (int i = 0; i < Settings::NativeInput::NUM_INPUTS; ++i) {

+ KeyMap::SetKeyMapping({Settings::values.input_mappings[Settings::NativeInput::All[i]], keyboard_id}, Service::HID::pad_mapping[i]);

+ }

+ for (int i = 0; i < Settings::NativeInput::NUM_INPUTS; ++i) {

+ KeyMap::SetKeyMapping({Settings::values.input_mappings[Settings::NativeInput::All[i]], keyboard_id}, Service::HID::pad_mapping[i]);

+ }

+static const std::array<QVariant, Settings::NativeInput::NUM_INPUTS> defaults = {

+ Qt::Key_A, Qt::Key_S, Qt::Key_Z, Qt::Key_X,

+ Qt::Key_Q, Qt::Key_W, Qt::Key_1, Qt::Key_2,

+ Qt::Key_M, Qt::Key_N, Qt::Key_B,

+ Qt::Key_T, Qt::Key_G, Qt::Key_F, Qt::Key_H,

+ Qt::Key_Up, Qt::Key_Down, Qt::Key_Left, Qt::Key_Right,

+ Qt::Key_I, Qt::Key_K, Qt::Key_J, Qt::Key_L

+};

+

+ for (int i = 0; i < Settings::NativeInput::NUM_INPUTS; ++i) {

+ Settings::values.input_mappings[Settings::NativeInput::All[i]] =

+ qt_config->value(QString::fromStdString(Settings::NativeInput::Mapping[i]), defaults[i]).toInt();

+ }

+ for (int i = 0; i < Settings::NativeInput::NUM_INPUTS; ++i) {

+ qt_config->setValue(QString::fromStdString(Settings::NativeInput::Mapping[i]),

+ Settings::values.input_mappings[Settings::NativeInput::All[i]]);

+ }

+ u32 next_instr = Core::g_app_core->GetPC();

+#include <QTreeView>

+ return 1;

+ if (index.column() == 0) {

+ { Pica::DebugContext::Event::PicaCommandLoaded, tr("Pica command loaded") },

+ { Pica::DebugContext::Event::PicaCommandProcessed, tr("Pica command processed") },

+ { Pica::DebugContext::Event::VertexLoaded, tr("Vertex loaded") },

+ { Pica::DebugContext::Event::IncomingDisplayTransfer, tr("Incoming display transfer") },

+ { Pica::DebugContext::Event::GSPCommandProcessed, tr("GSP command processed") },

+ { Pica::DebugContext::Event::BufferSwapped, tr("Buffers swapped") }

+ break;

+ }

+ case Qt::CheckStateRole:

+ {

+ if (index.column() == 0)

+ return data(index, Role_IsEnabled).toBool() ? Qt::Checked : Qt::Unchecked;

+Qt::ItemFlags BreakPointModel::flags(const QModelIndex &index) const

+ if (!index.isValid())

+ return 0;

+ Qt::ItemFlags flags = Qt::ItemIsEnabled;

+ if (index.column() == 0)

+ flags |= Qt::ItemIsUserCheckable;

+ return flags;

+

+ case Qt::CheckStateRole:

+ if (index.column() != 0)

+ return false;

+

+ context->breakpoints[event].enabled = value == Qt::Checked;

+ QModelIndex changed_index = createIndex(index.row(), 0);

+ createIndex(static_cast<int>(event), 0));

+ createIndex(static_cast<int>(active_breakpoint), 0));

+ breakpoint_list->setRootIsDecorated(false);

+ breakpoint_list->setHeaderHidden(true);

+ connect(breakpoint_list, SIGNAL(doubleClicked(const QModelIndex&)),

+ this, SLOT(OnItemDoubleClicked(const QModelIndex&)));

+

+void GraphicsBreakPointsWidget::OnItemDoubleClicked(const QModelIndex& index)

+ if (!index.isValid())

+ QModelIndex check_index = breakpoint_list->model()->index(index.row(), 0);

+ QVariant enabled = breakpoint_list->model()->data(check_index, Qt::CheckStateRole);

+ QVariant new_state = Qt::Unchecked;

+ if (enabled == Qt::Unchecked)

+ new_state = Qt::Checked;

+ breakpoint_list->model()->setData(check_index, new_state, Qt::CheckStateRole);

+ void OnItemDoubleClicked(const QModelIndex&);

+ Qt::ItemFlags flags(const QModelIndex &index) const;

+#include <QHeaderView>

+ return static_cast<int>(pica_trace.writes.size());

+ return 3;

+ switch ( index.column() ) {

+ case 0:

+ return QString::fromLatin1(Pica::Regs::GetCommandName(cmd.cmd_id).c_str());

+ case 1:

+ return QString("%1").arg(cmd.cmd_id, 3, 16, QLatin1Char('0'));

+ case 2:

+ return QString("%1").arg(val, 8, 16, QLatin1Char('0'));

+ switch (section) {

+ case 0:

+ case 1:

+ return tr("Register");

+ case 2:

+ return tr("New Value");

+ list_widget->setUniformRowHeights(true);

+

+#if QT_VERSION >= QT_VERSION_CHECK(5,0,0)

+ list_widget->header()->setSectionResizeMode(QHeaderView::ResizeToContents);

+#else

+ list_widget->header()->setResizeMode(QHeaderView::ResizeToContents);

+#endif

+ return static_cast<int>(info.code.size());

+ return static_cast<int>(results.time_per_category.size() + 2);

+void GMainWindow::BootGame(const std::string& filename) {

+ ui.action_Start->setText(tr("Start"));

+ ui.action_Start->setText(tr("Continue"));

+

+ void BootGame(const std::string& filename);

+ if (size == 0 || size != WideCharToMultiByte(CP_UTF8, 0, input.data(), static_cast<int>(input.size()), &output[0], static_cast<int>(output.size()), nullptr, nullptr))

+ arm/skyeye_common/armstate.cpp

+ arm/skyeye_common/armsupp.cpp

+ arm/skyeye_common/armstate.h

+ arm/skyeye_common/armsupp.h

+#include "core/arm/skyeye_common/armstate.h"

+#include "core/arm/skyeye_common/armsupp.h"

+ state = Common::make_unique<ARMul_State>(initial_mode);

+ memcpy(ctx.cpu_registers, state->Reg.data(), sizeof(ctx.cpu_registers));

+ memcpy(ctx.fpu_registers, state->ExtReg.data(), sizeof(ctx.fpu_registers));

+ memcpy(state->Reg.data(), ctx.cpu_registers, sizeof(ctx.cpu_registers));

+ memcpy(state->ExtReg.data(), ctx.fpu_registers, sizeof(ctx.fpu_registers));

+#include "core/arm/skyeye_common/armstate.h"

+#include "core/arm/skyeye_common/armsupp.h"

+const InstructionSetEncodingItem arm_instruction[] = {

+const InstructionSetEncodingItem arm_exclusion_code[] = {

+ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {

+ int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);

+ ARMDecodeStatus ret = ARMDecodeStatus::FAILURE;

+ for (int i = 0; i < instr_slots; i++) {

+ // All conditions are satisfied.

+ ret = ARMDecodeStatus::SUCCESS;

+ if (ret == ARMDecodeStatus::SUCCESS) {

+ // All conditions are satisfied.

+ ret = ARMDecodeStatus::FAILURE;

+ if (ret == ARMDecodeStatus::SUCCESS) {

+#include "common/common_types.h"

+enum class ARMDecodeStatus {

+ SUCCESS,

+ FAILURE

+ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx);

+

+struct InstructionSetEncodingItem {

+extern const InstructionSetEncodingItem arm_instruction[];

+#include "core/arm/skyeye_common/armstate.h"

+#include "core/arm/skyeye_common/armsupp.h"

+static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_inst, u32* inst_size, ARM_INST_PTR* ptr_inst_base) {

+ ThumbDecodeStatus ret = TranslateThumbInstruction (addr, inst, arm_inst, inst_size);

+ if (ret == ThumbDecodeStatus::BRANCH) {

+ u32 tinstr = GetThumbInstruction(inst, addr);

+ switch ((tinstr & 0xF800) >> 11) {

+ ret = ThumbDecodeStatus::UNDEFINED;

+ // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction

+ ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);

+ // We have translated the Thumb branch instruction in the Thumb decoder

+ if (state == ThumbDecodeStatus::BRANCH) {

+ if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {

+ u32 rn_val = RN;

+ if (inst_cream->Rn == 15)

+ rn_val += 2 * cpu->GetInstructionSize();

+

+ RD = AddWithCarry(rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ rn_val += 2 * cpu->GetInstructionSize();

+ cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {

+ and_inst* const inst_cream = (and_inst*)inst_base->component;

+

+

+ if (inst_cream->Rn == 15)

+ lop += 2 * cpu->GetInstructionSize();

+

+

+ cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ lop += 2 * cpu->GetInstructionSize();

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());

+ cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ address += 2 * cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->UnsetExclusiveMemoryAddress();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ u32 rn_val = RN;

+ if (inst_cream->Rn == 15)

+ rn_val += 2 * cpu->GetInstructionSize();

+

+ u32 result = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ rn_val += 2 * cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ if (cpu->InAPrivilegedMode()) {

+ cpu->ChangePrivilegeMode(inst_cream->mode);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ lop += 2 * cpu->GetInstructionSize();

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[i] = cpu->ReadMemory32(addr);

+ cpu->Reg[13] = cpu->ReadMemory32(addr);

+ cpu->Reg_usr[0] = cpu->ReadMemory32(addr);

+ cpu->Reg[14] = cpu->ReadMemory32(addr);

+ cpu->Reg_usr[1] = cpu->ReadMemory32(addr);

+ unsigned int ret = cpu->ReadMemory32(addr);

+ cpu->Reg[i] = cpu->ReadMemory32(addr);

+ cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);

+ cpu->Reg[15] = cpu->ReadMemory32(addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ unsigned int value = cpu->ReadMemory32(addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ unsigned int value = cpu->ReadMemory32(addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = cpu->ReadMemory32(addr);

+ cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = cpu->ReadMemory32(addr + 4);

+ cpu->SetExclusiveMemoryAddress(read_addr);

+ RD = cpu->ReadMemory32(read_addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->SetExclusiveMemoryAddress(read_addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->SetExclusiveMemoryAddress(read_addr);

+ RD = cpu->ReadMemory16(read_addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->SetExclusiveMemoryAddress(read_addr);

+ RD = cpu->ReadMemory32(read_addr);

+ RD2 = cpu->ReadMemory32(read_addr + 4);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ unsigned int value = cpu->ReadMemory16(addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ unsigned int value = cpu->ReadMemory32(addr);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteCP15Register(RD, CRn, OPCODE_1, CRm, OPCODE_2);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ RD = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ if (cpu->InAPrivilegedMode()) {

+ cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+

+ if (inst_cream->Rn == 15)

+ lop += 2 * cpu->GetInstructionSize();

+

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Cpsr = cpu->ReadMemory32(address);

+ cpu->Reg[15] = cpu->ReadMemory32(address + 4);

+ rn_val += 2 * cpu->GetInstructionSize();

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ u32 rn_val = RN;

+ if (inst_cream->Rn == 15)

+ rn_val += 2 * cpu->GetInstructionSize();

+

+ RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ u32 rn_val = RN;

+ if (inst_cream->Rn == 15)

+ rn_val += 2 * cpu->GetInstructionSize();

+

+ RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(address + 0, cpu->Reg[14]);

+ cpu->WriteMemory32(address + 4, cpu->Spsr_copy);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(addr, cpu->Reg[i]);

+ cpu->WriteMemory32(addr, cpu->Reg[13]);

+ cpu->WriteMemory32(addr, cpu->Reg_usr[0]);

+ cpu->WriteMemory32(addr, cpu->Reg[14]);

+ cpu->WriteMemory32(addr, cpu->Reg_usr[1]);

+ cpu->WriteMemory32(addr, cpu->Reg_usr[1] + 8);

+ cpu->WriteMemory32(addr, old_RN);

+ cpu->WriteMemory32(addr, cpu->Reg[i]);

+ cpu->WriteMemory32(addr, cpu->Reg_usr[1] + 8);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(addr, value);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]);

+ cpu->WriteMemory32(addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ if (cpu->IsExclusiveMemoryAccess(write_addr)) {

+ cpu->UnsetExclusiveMemoryAddress();

+ cpu->WriteMemory32(write_addr, RM);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ if (cpu->IsExclusiveMemoryAccess(write_addr)) {

+ cpu->UnsetExclusiveMemoryAddress();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ if (cpu->IsExclusiveMemoryAccess(write_addr)) {

+ cpu->UnsetExclusiveMemoryAddress();

+ if (cpu->InBigEndianMode())

+ cpu->WriteMemory64(write_addr, value);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ if (cpu->IsExclusiveMemoryAccess(write_addr)) {

+ cpu->UnsetExclusiveMemoryAddress();

+ cpu->WriteMemory16(write_addr, RM);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory16(addr, value);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(addr, value);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ rn_val += 2 * cpu->GetInstructionSize();

+ cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ unsigned int value = cpu->ReadMemory32(addr);

+ cpu->WriteMemory32(addr, RM);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ lop += cpu->GetInstructionSize() * 2;

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ lop += cpu->GetInstructionSize() * 2;

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+struct ARMul_State;

+#include "core/arm/skyeye_common/armstate.h"

+ * @param cpu The ARM CPU state instance.

+static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {

+ return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];

+ * @param cpu The ARM CPU state instance.

+static inline u32 CHECK_READ_REG15(ARMul_State* cpu, int Rn) {

+ return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];

+#include "core/arm/skyeye_common/armsupp.h"

+ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {

+ ThumbDecodeStatus valid = ThumbDecodeStatus::UNINITIALIZED;

+ u32 tinstr = GetThumbInstruction(instr, addr);

+ static const u32 subset[4] = {

+ static const u32 subset[4] = {

+ u32 opcode;

+ u32 Rd = ((tinstr & 0x0007) >> 0);

+ u32 Rs = ((tinstr & 0x0078) >> 3);

+ static const u32 subset[8] = {

+ static const u32 subset[4] = {

+ static const u32 subset[4] = {

+ static const u32 subset[3] = {

+ static const u32 subset[4] = {

+ valid = ThumbDecodeStatus::BRANCH;

+ valid = ThumbDecodeStatus::UNDEFINED;

+ valid = ThumbDecodeStatus::BRANCH;

+ if (tinstr & 0x1)

+ valid = ThumbDecodeStatus::UNDEFINED;

+ valid = ThumbDecodeStatus::BRANCH;

+ valid = ThumbDecodeStatus::BRANCH;

+ valid = ThumbDecodeStatus::BRANCH;

+#include "common/common_types.h"

+enum class ThumbDecodeStatus {

+ UNDEFINED, // Undefined Thumb instruction

+ DECODED, // Instruction decoded to ARM equivalent

+ BRANCH, // Thumb branch (already processed)

+ UNINITIALIZED,

+// Translates a Thumb mode instruction into its ARM equivalent.

+ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size);

+static inline u32 GetThumbInstruction(u32 instr, u32 address) {

+ // Normally you would need to handle instruction endianness,

+ // however, it is fixed to little-endian on the MPCore, so

+ // there's no need to check for this beforehand.

+ if ((address & 0x3) != 0)

+ return instr >> 16;

+

+ return instr & 0xFFFF;

+// Copyright 2015 Citra Emulator Project

+// Licensed under GPLv2 or any later version

+// Refer to the license.txt file included.

+

+#include "common/swap.h"

+#include "common/logging/log.h"

+#include "core/mem_map.h"

+#include "core/memory.h"

+#include "core/arm/skyeye_common/armstate.h"

+#include "core/arm/skyeye_common/vfp/vfp.h"

+

+ARMul_State::ARMul_State(PrivilegeMode initial_mode)

+{

+ Reset();

+ ChangePrivilegeMode(initial_mode);

+}

+

+void ARMul_State::ChangePrivilegeMode(u32 new_mode)

+{

+ if (Mode == new_mode)

+ return;

+

+ if (new_mode != USERBANK) {

+ switch (Mode) {

+ case SYSTEM32MODE: // Shares registers with user mode

+ case USER32MODE:

+ Reg_usr[0] = Reg[13];

+ Reg_usr[1] = Reg[14];

+ break;

+ case IRQ32MODE:

+ Reg_irq[0] = Reg[13];

+ Reg_irq[1] = Reg[14];

+ Spsr[IRQBANK] = Spsr_copy;

+ break;

+ case SVC32MODE:

+ Reg_svc[0] = Reg[13];

+ Reg_svc[1] = Reg[14];

+ Spsr[SVCBANK] = Spsr_copy;

+ break;

+ case ABORT32MODE:

+ Reg_abort[0] = Reg[13];

+ Reg_abort[1] = Reg[14];

+ Spsr[ABORTBANK] = Spsr_copy;

+ break;

+ case UNDEF32MODE:

+ Reg_undef[0] = Reg[13];

+ Reg_undef[1] = Reg[14];

+ Spsr[UNDEFBANK] = Spsr_copy;

+ break;

+ case FIQ32MODE:

+ Reg_firq[0] = Reg[13];

+ Reg_firq[1] = Reg[14];

+ Spsr[FIQBANK] = Spsr_copy;

+ break;

+ }

+

+ switch (new_mode) {

+ case USER32MODE:

+ Reg[13] = Reg_usr[0];

+ Reg[14] = Reg_usr[1];

+ Bank = USERBANK;

+ break;

+ case IRQ32MODE:

+ Reg[13] = Reg_irq[0];

+ Reg[14] = Reg_irq[1];

+ Spsr_copy = Spsr[IRQBANK];

+ Bank = IRQBANK;

+ break;

+ case SVC32MODE:

+ Reg[13] = Reg_svc[0];

+ Reg[14] = Reg_svc[1];

+ Spsr_copy = Spsr[SVCBANK];

+ Bank = SVCBANK;

+ break;

+ case ABORT32MODE:

+ Reg[13] = Reg_abort[0];

+ Reg[14] = Reg_abort[1];

+ Spsr_copy = Spsr[ABORTBANK];

+ Bank = ABORTBANK;

+ break;

+ case UNDEF32MODE:

+ Reg[13] = Reg_undef[0];

+ Reg[14] = Reg_undef[1];

+ Spsr_copy = Spsr[UNDEFBANK];

+ Bank = UNDEFBANK;

+ break;

+ case FIQ32MODE:

+ Reg[13] = Reg_firq[0];

+ Reg[14] = Reg_firq[1];

+ Spsr_copy = Spsr[FIQBANK];

+ Bank = FIQBANK;

+ break;

+ case SYSTEM32MODE: // Shares registers with user mode.

+ Reg[13] = Reg_usr[0];

+ Reg[14] = Reg_usr[1];

+ Bank = SYSTEMBANK;

+ break;

+ }

+

+ // Set the mode bits in the APSR

+ Cpsr = (Cpsr & ~Mode) | new_mode;

+ Mode = new_mode;

+ }

+}

+

+// Performs a reset

+void ARMul_State::Reset()

+{

+ VFPInit(this);

+

+ // Set stack pointer to the top of the stack

+ Reg[13] = 0x10000000;

+ Reg[15] = 0;

+

+ Cpsr = INTBITS | SVC32MODE;

+ Mode = SVC32MODE;

+ Bank = SVCBANK;

+

+ ResetMPCoreCP15Registers();

+

+ NresetSig = HIGH;

+ NfiqSig = HIGH;

+ NirqSig = HIGH;

+ NtransSig = (Mode & 3) ? HIGH : LOW;

+ abortSig = LOW;

+

+ NumInstrs = 0;

+ Emulate = RUN;

+}

+

+// Resets certain MPCore CP15 values to their ARM-defined reset values.

+void ARMul_State::ResetMPCoreCP15Registers()

+{

+ // c0

+ CP15[CP15_MAIN_ID] = 0x410FB024;

+ CP15[CP15_TLB_TYPE] = 0x00000800;

+ CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111;

+ CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001;

+ CP15[CP15_DEBUG_FEATURE_0] = 0x00000002;

+ CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103;

+ CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302;

+ CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000;

+ CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000;

+ CP15[CP15_ISA_FEATURE_0] = 0x00100011;

+ CP15[CP15_ISA_FEATURE_1] = 0x12002111;

+ CP15[CP15_ISA_FEATURE_2] = 0x11221011;

+ CP15[CP15_ISA_FEATURE_3] = 0x01102131;

+ CP15[CP15_ISA_FEATURE_4] = 0x00000141;

+

+ // c1

+ CP15[CP15_CONTROL] = 0x00054078;

+ CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F;

+ CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000;

+

+ // c2

+ CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000;

+ CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000;

+ CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000;

+

+ // c3

+ CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000;

+

+ // c7

+ CP15[CP15_PHYS_ADDRESS] = 0x00000000;

+

+ // c9

+ CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0;

+

+ // c10

+ CP15[CP15_TLB_LOCKDOWN] = 0x00000000;

+ CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4;

+ CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0;

+

+ // c13

+ CP15[CP15_PID] = 0x00000000;

+ CP15[CP15_CONTEXT_ID] = 0x00000000;

+ CP15[CP15_THREAD_UPRW] = 0x00000000;

+ CP15[CP15_THREAD_URO] = 0x00000000;

+ CP15[CP15_THREAD_PRW] = 0x00000000;

+

+ // c15

+ CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000;

+ CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000;

+ CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000;

+ CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000;

+ CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;

+}

+

+u16 ARMul_State::ReadMemory16(u32 address) const

+{

+ u16 data = Memory::Read16(address);

+

+ if (InBigEndianMode())

+ data = Common::swap16(data);

+

+ return data;

+}

+

+u32 ARMul_State::ReadMemory32(u32 address) const

+{

+ u32 data = Memory::Read32(address);

+

+ if (InBigEndianMode())

+ data = Common::swap32(data);

+

+ return data;

+}

+

+u64 ARMul_State::ReadMemory64(u32 address) const

+{

+ u64 data = Memory::Read64(address);

+

+ if (InBigEndianMode())

+ data = Common::swap64(data);

+

+ return data;

+}

+

+void ARMul_State::WriteMemory16(u32 address, u16 data)

+{

+ if (InBigEndianMode())

+ data = Common::swap16(data);

+

+ Memory::Write16(address, data);

+}

+

+void ARMul_State::WriteMemory32(u32 address, u32 data)

+{

+ if (InBigEndianMode())

+ data = Common::swap32(data);

+

+ Memory::Write32(address, data);

+}

+

+void ARMul_State::WriteMemory64(u32 address, u64 data)

+{

+ if (InBigEndianMode())

+ data = Common::swap64(data);

+

+ Memory::Write64(address, data);

+}

+

+

+// Reads from the CP15 registers. Used with implementation of the MRC instruction.

+// Note that since the 3DS does not have the hypervisor extensions, these registers

+// are not implemented.

+u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const

+{

+ // Unprivileged registers

+ if (crn == 13 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 2)

+ return CP15[CP15_THREAD_UPRW];

+

+ if (opcode_2 == 3)

+ return CP15[CP15_THREAD_URO];

+ }

+

+ if (InAPrivilegedMode())

+ {

+ if (crn == 0 && opcode_1 == 0)

+ {

+ if (crm == 0)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_MAIN_ID];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_CACHE_TYPE];

+

+ if (opcode_2 == 3)

+ return CP15[CP15_TLB_TYPE];

+

+ if (opcode_2 == 5)

+ return CP15[CP15_CPU_ID];

+ }

+ else if (crm == 1)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_PROCESSOR_FEATURE_0];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_PROCESSOR_FEATURE_1];

+

+ if (opcode_2 == 2)

+ return CP15[CP15_DEBUG_FEATURE_0];

+

+ if (opcode_2 == 4)

+ return CP15[CP15_MEMORY_MODEL_FEATURE_0];

+

+ if (opcode_2 == 5)

+ return CP15[CP15_MEMORY_MODEL_FEATURE_1];

+

+ if (opcode_2 == 6)

+ return CP15[CP15_MEMORY_MODEL_FEATURE_2];

+

+ if (opcode_2 == 7)

+ return CP15[CP15_MEMORY_MODEL_FEATURE_3];

+ }

+ else if (crm == 2)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_ISA_FEATURE_0];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_ISA_FEATURE_1];

+

+ if (opcode_2 == 2)

+ return CP15[CP15_ISA_FEATURE_2];

+

+ if (opcode_2 == 3)

+ return CP15[CP15_ISA_FEATURE_3];

+

+ if (opcode_2 == 4)

+ return CP15[CP15_ISA_FEATURE_4];

+ }

+ }

+

+ if (crn == 1 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_CONTROL];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_AUXILIARY_CONTROL];

+

+ if (opcode_2 == 2)

+ return CP15[CP15_COPROCESSOR_ACCESS_CONTROL];

+ }

+

+ if (crn == 2 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_TRANSLATION_BASE_TABLE_0];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_TRANSLATION_BASE_TABLE_1];

+

+ if (opcode_2 == 2)

+ return CP15[CP15_TRANSLATION_BASE_CONTROL];

+ }

+

+ if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)

+ return CP15[CP15_DOMAIN_ACCESS_CONTROL];

+

+ if (crn == 5 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_FAULT_STATUS];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_INSTR_FAULT_STATUS];

+ }

+

+ if (crn == 6 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_FAULT_ADDRESS];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_WFAR];

+ }

+

+ if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)

+ return CP15[CP15_PHYS_ADDRESS];

+

+ if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)

+ return CP15[CP15_DATA_CACHE_LOCKDOWN];

+

+ if (crn == 10 && opcode_1 == 0)

+ {

+ if (crm == 0 && opcode_2 == 0)

+ return CP15[CP15_TLB_LOCKDOWN];

+

+ if (crm == 2)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_PRIMARY_REGION_REMAP];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_NORMAL_REGION_REMAP];

+ }

+ }

+

+ if (crn == 13 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_PID];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_CONTEXT_ID];

+

+ if (opcode_2 == 4)

+ return CP15[CP15_THREAD_PRW];

+ }

+

+ if (crn == 15)

+ {

+ if (opcode_1 == 0 && crm == 12)

+ {

+ if (opcode_2 == 0)

+ return CP15[CP15_PERFORMANCE_MONITOR_CONTROL];

+

+ if (opcode_2 == 1)

+ return CP15[CP15_CYCLE_COUNTER];

+

+ if (opcode_2 == 2)

+ return CP15[CP15_COUNT_0];

+

+ if (opcode_2 == 3)

+ return CP15[CP15_COUNT_1];

+ }

+

+ if (opcode_1 == 5 && opcode_2 == 2)

+ {

+ if (crm == 5)

+ return CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS];

+

+ if (crm == 6)

+ return CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS];

+

+ if (crm == 7)

+ return CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE];

+ }

+

+ if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)

+ return CP15[CP15_TLB_DEBUG_CONTROL];

+ }

+ }

+

+ LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);

+ return 0;

+}

+

+// Write to the CP15 registers. Used with implementation of the MCR instruction.

+// Note that since the 3DS does not have the hypervisor extensions, these registers

+// are not implemented.

+void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)

+{

+ if (InAPrivilegedMode())

+ {

+ if (crn == 1 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_CONTROL] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_AUXILIARY_CONTROL] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value;

+ }

+ else if (crn == 2 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_TRANSLATION_BASE_TABLE_0] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_TRANSLATION_BASE_TABLE_1] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_TRANSLATION_BASE_CONTROL] = value;

+ }

+ else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)

+ {

+ CP15[CP15_DOMAIN_ACCESS_CONTROL] = value;

+ }

+ else if (crn == 5 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_FAULT_STATUS] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_INSTR_FAULT_STATUS] = value;

+ }

+ else if (crn == 6 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_FAULT_ADDRESS] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_WFAR] = value;

+ }

+ else if (crn == 7 && opcode_1 == 0)

+ {

+ if (crm == 0 && opcode_2 == 4)

+ {

+ CP15[CP15_WAIT_FOR_INTERRUPT] = value;

+ }

+ else if (crm == 4 && opcode_2 == 0)

+ {

+ // NOTE: Not entirely accurate. This should do permission checks.

+ CP15[CP15_PHYS_ADDRESS] = Memory::VirtualToPhysicalAddress(value);

+ }

+ else if (crm == 5)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_INVALIDATE_INSTR_CACHE] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_INVALIDATE_INSTR_CACHE_USING_MVA] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_INVALIDATE_INSTR_CACHE_USING_INDEX] = value;

+ else if (opcode_2 == 6)

+ CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value;

+ else if (opcode_2 == 7)

+ CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value;

+ }

+ else if (crm == 6)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_INVALIDATE_DATA_CACHE] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;

+ }

+ else if (crm == 7 && opcode_2 == 0)

+ {

+ CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value;

+ }

+ else if (crm == 10)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_CLEAN_DATA_CACHE] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value;

+ }

+ else if (crm == 14)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;

+ }

+ }

+ else if (crn == 8 && opcode_1 == 0)

+ {

+ if (crm == 5)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_INVALIDATE_ITLB] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_INVALIDATE_ITLB_SINGLE_ENTRY] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value;

+ else if (opcode_2 == 3)

+ CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value;

+ }

+ else if (crm == 6)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_INVALIDATE_DTLB] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_INVALIDATE_DTLB_SINGLE_ENTRY] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value;

+ else if (opcode_2 == 3)

+ CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value;

+ }

+ else if (crm == 7)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_INVALIDATE_UTLB] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_INVALIDATE_UTLB_SINGLE_ENTRY] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH] = value;

+ else if (opcode_2 == 3)

+ CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value;

+ }

+ }

+ else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)

+ {

+ CP15[CP15_DATA_CACHE_LOCKDOWN] = value;

+ }

+ else if (crn == 10 && opcode_1 == 0)

+ {

+ if (crm == 0 && opcode_2 == 0)

+ {

+ CP15[CP15_TLB_LOCKDOWN] = value;

+ }

+ else if (crm == 2)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_PRIMARY_REGION_REMAP] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_NORMAL_REGION_REMAP] = value;

+ }

+ }

+ else if (crn == 13 && opcode_1 == 0 && crm == 0)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_PID] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_CONTEXT_ID] = value;

+ else if (opcode_2 == 3)

+ CP15[CP15_THREAD_URO] = value;

+ else if (opcode_2 == 4)

+ CP15[CP15_THREAD_PRW] = value;

+ }

+ else if (crn == 15)

+ {

+ if (opcode_1 == 0 && crm == 12)

+ {

+ if (opcode_2 == 0)

+ CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value;

+ else if (opcode_2 == 1)

+ CP15[CP15_CYCLE_COUNTER] = value;

+ else if (opcode_2 == 2)

+ CP15[CP15_COUNT_0] = value;

+ else if (opcode_2 == 3)

+ CP15[CP15_COUNT_1] = value;

+ }

+ else if (opcode_1 == 5)

+ {

+ if (crm == 4)

+ {

+ if (opcode_2 == 2)

+ CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value;

+ else if (opcode_2 == 4)

+ CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value;

+ }

+ else if (crm == 5 && opcode_2 == 2)

+ {

+ CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value;

+ }

+ else if (crm == 6 && opcode_2 == 2)

+ {

+ CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value;

+ }

+ else if (crm == 7 && opcode_2 == 2)

+ {

+ CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value;

+ }

+ }

+ else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)

+ {

+ CP15[CP15_TLB_DEBUG_CONTROL] = value;

+ }

+ }

+ }

+

+ // Unprivileged registers

+ if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4)

+ {

+ CP15[CP15_FLUSH_PREFETCH_BUFFER] = value;

+ }

+ else if (crn == 7 && opcode_1 == 0 && crm == 10)

+ {

+ if (opcode_2 == 4)

+ CP15[CP15_DATA_SYNC_BARRIER] = value;

+ else if (opcode_2 == 5)

+ CP15[CP15_DATA_MEMORY_BARRIER] = value;

+ }

+ else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)

+ {

+ CP15[CP15_THREAD_UPRW] = value;

+ }

+}

+/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.

+ Copyright (C) 1994 Advanced RISC Machines Ltd.

+

+ This program is free software; you can redistribute it and/or modify

+ it under the terms of the GNU General Public License as published by

+ the Free Software Foundation; either version 2 of the License, or

+ (at your option) any later version.

+

+ This program is distributed in the hope that it will be useful,

+ but WITHOUT ANY WARRANTY; without even the implied warranty of

+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ GNU General Public License for more details.

+

+ You should have received a copy of the GNU General Public License

+ along with this program; if not, write to the Free Software

+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

+

+#pragma once

+

+#include <array>

+#include <unordered_map>

+

+#include "common/common_types.h"

+#include "core/arm/skyeye_common/arm_regformat.h"

+

+// Signal levels

+enum {

+ LOW = 0,

+ HIGH = 1,

+ LOWHIGH = 1,

+ HIGHLOW = 2

+};

+

+// Cache types

+enum {

+ NONCACHE = 0,

+ DATACACHE = 1,

+ INSTCACHE = 2,

+};

+

+// ARM privilege modes

+enum PrivilegeMode {

+ USER32MODE = 16,

+ FIQ32MODE = 17,

+ IRQ32MODE = 18,

+ SVC32MODE = 19,

+ ABORT32MODE = 23,

+ UNDEF32MODE = 27,

+ SYSTEM32MODE = 31

+};

+

+// ARM privilege mode register banks

+enum {

+ USERBANK = 0,

+ FIQBANK = 1,

+ IRQBANK = 2,

+ SVCBANK = 3,

+ ABORTBANK = 4,

+ UNDEFBANK = 5,

+ DUMMYBANK = 6,

+ SYSTEMBANK = 7

+};

+

+// Hardware vector addresses

+enum {

+ ARMResetV = 0,

+ ARMUndefinedInstrV = 4,

+ ARMSWIV = 8,

+ ARMPrefetchAbortV = 12,

+ ARMDataAbortV = 16,

+ ARMAddrExceptnV = 20,

+ ARMIRQV = 24,

+ ARMFIQV = 28,

+ ARMErrorV = 32, // This is an offset, not an address!

+

+ ARMul_ResetV = ARMResetV,

+ ARMul_UndefinedInstrV = ARMUndefinedInstrV,

+ ARMul_SWIV = ARMSWIV,

+ ARMul_PrefetchAbortV = ARMPrefetchAbortV,

+ ARMul_DataAbortV = ARMDataAbortV,

+ ARMul_AddrExceptnV = ARMAddrExceptnV,

+ ARMul_IRQV = ARMIRQV,

+ ARMul_FIQV = ARMFIQV

+};

+

+// Coprocessor status values

+enum {

+ ARMul_FIRST = 0,

+ ARMul_TRANSFER = 1,

+ ARMul_BUSY = 2,

+ ARMul_DATA = 3,

+ ARMul_INTERRUPT = 4,

+ ARMul_DONE = 0,

+ ARMul_CANT = 1,

+ ARMul_INC = 3

+};

+

+// Instruction condition codes

+enum ConditionCode {

+ EQ = 0,

+ NE = 1,

+ CS = 2,

+ CC = 3,

+ MI = 4,

+ PL = 5,

+ VS = 6,

+ VC = 7,

+ HI = 8,

+ LS = 9,

+ GE = 10,

+ LT = 11,

+ GT = 12,

+ LE = 13,

+ AL = 14,

+ NV = 15,

+};

+

+// Flags for use with the APSR.

+enum : u32 {

+ NBIT = (1U << 31U),

+ ZBIT = (1 << 30),

+ CBIT = (1 << 29),

+ VBIT = (1 << 28),

+ QBIT = (1 << 27),

+ JBIT = (1 << 24),

+ EBIT = (1 << 9),

+ ABIT = (1 << 8),

+ IBIT = (1 << 7),

+ FBIT = (1 << 6),

+ TBIT = (1 << 5),

+

+ // Masks for groups of bits in the APSR.

+ MODEBITS = 0x1F,

+ INTBITS = 0x1C0,

+};

+

+// Values for Emulate.

+enum {

+ STOP = 0, // Stop

+ CHANGEMODE = 1, // Change mode

+ ONCE = 2, // Execute just one iteration

+ RUN = 3 // Continuous execution

+};

+

+

+struct ARMul_State final

+{

+public:

+ explicit ARMul_State(PrivilegeMode initial_mode);

+

+ void ChangePrivilegeMode(u32 new_mode);

+ void Reset();

+

+ // Reads/writes data in big/little endian format based on the

+ // state of the E (endian) bit in the APSR.

+ u16 ReadMemory16(u32 address) const;

+ u32 ReadMemory32(u32 address) const;

+ u64 ReadMemory64(u32 address) const;

+ void WriteMemory16(u32 address, u16 data);

+ void WriteMemory32(u32 address, u32 data);

+ void WriteMemory64(u32 address, u64 data);

+

+ u32 ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const;

+ void WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);

+

+ // Exclusive memory access functions

+ bool IsExclusiveMemoryAccess(u32 address) const {

+ return exclusive_state && exclusive_tag == (address & RESERVATION_GRANULE_MASK);

+ }

+ void SetExclusiveMemoryAddress(u32 address) {

+ exclusive_tag = address & RESERVATION_GRANULE_MASK;

+ exclusive_state = true;

+ }

+ void UnsetExclusiveMemoryAddress() {

+ exclusive_tag = 0xFFFFFFFF;

+ exclusive_state = false;

+ }

+

+ // Whether or not the given CPU is in big endian mode (E bit is set)

+ bool InBigEndianMode() const {

+ return (Cpsr & (1 << 9)) != 0;

+ }

+ // Whether or not the given CPU is in a mode other than user mode.

+ bool InAPrivilegedMode() const {

+ return (Mode != USER32MODE);

+ }

+ // Note that for the 3DS, a Thumb instruction will only ever be

+ // two bytes in size. Thus we don't need to worry about ThumbEE

+ // or Thumb-2 where instructions can be 4 bytes in length.

+ u32 GetInstructionSize() const {

+ return TFlag ? 2 : 4;

+ }

+

+ std::array<u32, 16> Reg; // The current register file

+ std::array<u32, 2> Reg_usr;

+ std::array<u32, 2> Reg_svc; // R13_SVC R14_SVC

+ std::array<u32, 2> Reg_abort; // R13_ABORT R14_ABORT

+ std::array<u32, 2> Reg_undef; // R13 UNDEF R14 UNDEF

+ std::array<u32, 2> Reg_irq; // R13_IRQ R14_IRQ

+ std::array<u32, 7> Reg_firq; // R8---R14 FIRQ

+ std::array<u32, 7> Spsr; // The exception psr's

+ std::array<u32, CP15_REGISTER_COUNT> CP15;

+

+ // FPSID, FPSCR, and FPEXC

+ std::array<u32, VFP_SYSTEM_REGISTER_COUNT> VFP;

+

+ // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).

+ // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),

+ // and only 32 singleword registers are accessible (S0-S31).

+ std::array<u32, 64> ExtReg;

+

+ u32 Emulate; // To start and stop emulation

+ u32 Cpsr; // The current PSR

+ u32 Spsr_copy;

+ u32 phys_pc;

+

+ u32 Mode; // The current mode

+ u32 Bank; // The current register bank

+

+ u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed

+ unsigned int shifter_carry_out;

+

+ u32 TFlag; // Thumb state

+

+ unsigned long long NumInstrs; // The number of instructions executed

+ unsigned NumInstrsToExecute;

+

+ unsigned NresetSig; // Reset the processor

+ unsigned NfiqSig;

+ unsigned NirqSig;

+

+ unsigned abortSig;

+ unsigned NtransSig;

+ unsigned bigendSig;

+ unsigned syscallSig;

+

+ // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per

+ // process for our purposes), not per ARMul_State (which tracks CPU core state).

+ std::unordered_map<u32, int> instruction_cache;

+

+private:

+ void ResetMPCoreCP15Registers();

+

+ // Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.

+ // This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to

+ // support LDR/STREXD.

+ static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;

+

+ u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode

+ u32 exclusive_result;

+ bool exclusive_state;

+};

+/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.

+ Copyright (C) 1994 Advanced RISC Machines Ltd.

+

+ This program is free software; you can redistribute it and/or modify

+ it under the terms of the GNU General Public License as published by

+ the Free Software Foundation; either version 2 of the License, or

+ (at your option) any later version.

+

+ This program is distributed in the hope that it will be useful,

+ but WITHOUT ANY WARRANTY; without even the implied warranty of

+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ GNU General Public License for more details.

+

+ You should have received a copy of the GNU General Public License

+ along with this program; if not, write to the Free Software

+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

+

+#include "common/logging/log.h"

+

+#include "core/mem_map.h"

+#include "core/arm/skyeye_common/arm_regformat.h"

+#include "core/arm/skyeye_common/armstate.h"

+#include "core/arm/skyeye_common/armsupp.h"

+

+// Unsigned sum of absolute difference

+u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)

+{

+ if (left > right)

+ return left - right;

+

+ return right - left;

+}

+

+// Add with carry, indicates if a carry-out or signed overflow occurred.

+u32 AddWithCarry(u32 left, u32 right, u32 carry_in, bool* carry_out_occurred, bool* overflow_occurred)

+{

+ u64 unsigned_sum = (u64)left + (u64)right + (u64)carry_in;

+ s64 signed_sum = (s64)(s32)left + (s64)(s32)right + (s64)carry_in;

+ u64 result = (unsigned_sum & 0xFFFFFFFF);

+

+ if (carry_out_occurred)

+ *carry_out_occurred = (result != unsigned_sum);

+

+ if (overflow_occurred)

+ *overflow_occurred = ((s64)(s32)result != signed_sum);

+

+ return (u32)result;

+}

+

+// Compute whether an addition of A and B, giving RESULT, overflowed.

+bool AddOverflow(u32 a, u32 b, u32 result)

+{

+ return ((NEG(a) && NEG(b) && POS(result)) ||

+ (POS(a) && POS(b) && NEG(result)));

+}

+

+// Compute whether a subtraction of A and B, giving RESULT, overflowed.

+bool SubOverflow(u32 a, u32 b, u32 result)

+{

+ return ((NEG(a) && POS(b) && POS(result)) ||

+ (POS(a) && NEG(b) && NEG(result)));

+}

+

+// Returns true if the Q flag should be set as a result of overflow.

+bool ARMul_AddOverflowQ(u32 a, u32 b)

+{

+ u32 result = a + b;

+ if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0)

+ return true;

+

+ return false;

+}

+

+// 8-bit signed saturated addition

+u8 ARMul_SignedSaturatedAdd8(u8 left, u8 right)

+{

+ u8 result = left + right;

+

+ if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) == 0) {

+ if (left & 0x80)

+ result = 0x80;

+ else

+ result = 0x7F;

+ }

+

+ return result;

+}

+

+// 8-bit signed saturated subtraction

+u8 ARMul_SignedSaturatedSub8(u8 left, u8 right)

+{

+ u8 result = left - right;

+

+ if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) != 0) {

+ if (left & 0x80)

+ result = 0x80;

+ else

+ result = 0x7F;

+ }

+

+ return result;

+}

+

+// 16-bit signed saturated addition

+u16 ARMul_SignedSaturatedAdd16(u16 left, u16 right)

+{

+ u16 result = left + right;

+

+ if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) == 0) {

+ if (left & 0x8000)

+ result = 0x8000;

+ else

+ result = 0x7FFF;

+ }

+

+ return result;

+}

+

+// 16-bit signed saturated subtraction

+u16 ARMul_SignedSaturatedSub16(u16 left, u16 right)

+{

+ u16 result = left - right;

+

+ if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) != 0) {

+ if (left & 0x8000)

+ result = 0x8000;

+ else

+ result = 0x7FFF;

+ }

+

+ return result;

+}

+

+// 8-bit unsigned saturated addition

+u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right)

+{

+ u8 result = left + right;

+

+ if (result < left)

+ result = 0xFF;

+

+ return result;

+}

+

+// 16-bit unsigned saturated addition

+u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right)

+{

+ u16 result = left + right;

+

+ if (result < left)

+ result = 0xFFFF;

+

+ return result;

+}

+

+// 8-bit unsigned saturated subtraction

+u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right)

+{

+ if (left <= right)

+ return 0;

+

+ return left - right;

+}

+

+// 16-bit unsigned saturated subtraction

+u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right)

+{

+ if (left <= right)

+ return 0;

+

+ return left - right;

+}

+

+// Signed saturation.

+u32 ARMul_SignedSatQ(s32 value, u8 shift, bool* saturation_occurred)

+{

+ const u32 max = (1 << shift) - 1;

+ const s32 top = (value >> shift);

+

+ if (top > 0) {

+ *saturation_occurred = true;

+ return max;

+ }

+ else if (top < -1) {

+ *saturation_occurred = true;

+ return ~max;

+ }

+

+ *saturation_occurred = false;

+ return (u32)value;

+}

+

+// Unsigned saturation

+u32 ARMul_UnsignedSatQ(s32 value, u8 shift, bool* saturation_occurred)

+{

+ const u32 max = (1 << shift) - 1;

+

+ if (value < 0) {

+ *saturation_occurred = true;

+ return 0;

+ } else if ((u32)value > max) {

+ *saturation_occurred = true;

+ return max;

+ }

+

+ *saturation_occurred = false;

+ return (u32)value;

+}

+// Copyright 2014 Citra Emulator Project

+// Licensed under GPLv2 or any later version

+// Refer to the license.txt file included.

+

+#pragma once

+

+#include "common/common_types.h"

+

+#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))

+#define BIT(s, n) ((s >> (n)) & 1)

+

+#define POS(i) ( (~(i)) >> 31 )

+#define NEG(i) ( (i) >> 31 )

+

+bool AddOverflow(u32, u32, u32);

+bool SubOverflow(u32, u32, u32);

+

+u32 AddWithCarry(u32, u32, u32, bool*, bool*);

+bool ARMul_AddOverflowQ(u32, u32);

+

+u8 ARMul_SignedSaturatedAdd8(u8, u8);

+u8 ARMul_SignedSaturatedSub8(u8, u8);

+u16 ARMul_SignedSaturatedAdd16(u16, u16);

+u16 ARMul_SignedSaturatedSub16(u16, u16);

+

+u8 ARMul_UnsignedSaturatedAdd8(u8, u8);

+u16 ARMul_UnsignedSaturatedAdd16(u16, u16);

+u8 ARMul_UnsignedSaturatedSub8(u8, u8);

+u16 ARMul_UnsignedSaturatedSub16(u16, u16);

+u8 ARMul_UnsignedAbsoluteDifference(u8, u8);

+u32 ARMul_SignedSatQ(s32, u8, bool*);

+u32 ARMul_UnsignedSatQ(s32, u8, bool*);

+#include "core/arm/skyeye_common/armstate.h"

+void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value)

+void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)

+void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)

+void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm)

+void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)

+void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value);

+void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);

+void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);

+void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm);

+void VMOVR(ARMul_State* state, u32 single, u32 d, u32 imm);

+#include "core/arm/skyeye_common/armstate.h"

+static inline u32 fls(u32 x)

+ int bits = 31 - fls((u32)(vd->significand >> 32));

+ bits = 63 - fls((u32)vd->significand);

+ shift = 32 - fls((u32)(significand >> 32));

+ shift = 64 - fls((u32)significand);

+ d = (u32)((vdm.significand << 1) >> shift);

+ d = (u32)((vdm.significand << 1) >> shift);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ else if (cpu->InAPrivilegedMode())

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ else if (cpu->InAPrivilegedMode())

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d]);

+ if (cpu->InBigEndianMode()) {

+ cpu->WriteMemory32(addr + 0, word2);

+ cpu->WriteMemory32(addr + 4, word1);

+ cpu->WriteMemory32(addr + 0, word1);

+ cpu->WriteMemory32(addr + 4, word2);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d+i]);

+ if (cpu->InBigEndianMode()) {

+ cpu->WriteMemory32(addr + 0, word2);

+ cpu->WriteMemory32(addr + 4, word1);

+ cpu->WriteMemory32(addr + 0, word1);

+ cpu->WriteMemory32(addr + 4, word2);

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d+i]);

+ if (cpu->InBigEndianMode()) {

+ cpu->WriteMemory32(addr + 0, word2);

+ cpu->WriteMemory32(addr + 4, word1);

+ cpu->WriteMemory32(addr + 0, word1);

+ cpu->WriteMemory32(addr + 4, word2);

+ cpu->ExtReg[inst_cream->d+i] = cpu->ReadMemory32(addr);

+ const u32 word1 = cpu->ReadMemory32(addr + 0);

+ const u32 word2 = cpu->ReadMemory32(addr + 4);

+ if (cpu->InBigEndianMode()) {

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->ExtReg[inst_cream->d] = cpu->ReadMemory32(addr);

+ const u32 word1 = cpu->ReadMemory32(addr + 0);

+ const u32 word2 = cpu->ReadMemory32(addr + 4);

+ if (cpu->InBigEndianMode()) {

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ cpu->ExtReg[inst_cream->d+i] = cpu->ReadMemory32(addr);

+ const u32 word1 = cpu->ReadMemory32(addr + 0);

+ const u32 word2 = cpu->ReadMemory32(addr + 4);

+ if (cpu->InBigEndianMode()) {

+ cpu->Reg[15] += cpu->GetInstructionSize();

+ advance_callback(static_cast<int>(cycles_executed));

+bool IsLibraryAppletRunning() {

+ // Check the applets map for instances of any applet

+ for (auto itr = applets.begin(); itr != applets.end(); ++itr)

+ if (itr->second != nullptr)

+ return true;

+ return false;

+}

+

+ CoreTiming::RemoveEvent(applet_update_event);

+/// Returns whether a library applet is currently running

+bool IsLibraryAppletRunning();

+

+template<ResultCode func(s64*, u32, u32*, u32)> void Wrap(){

+#include "core/arm/skyeye_common/armstate.h"

+#include "core/hle/service/am/am.h"

+ {0x08180042, nullptr, "GetCTCert"},

+ {0x08190108, nullptr, "SetCertificates"},

+ // Bits [0:2] are the applet type (System, Library, etc)

+ // Bit 5 tells the application that there's a pending APT parameter,

+ // this will cause the app to wait until parameter_event is signaled.

+ u32 applet_attributes = cmd_buff[1];

+ cmd_buff[2] = applet_attributes; // Applet Attributes, this value is passed to Enable.

+ cmd_buff[3] = 0; // Least significant bit = power button state

+ cmd_buff[4] = IPC::CopyHandleDesc();

+

+ LOG_WARNING(Service_APT, "(STUBBED) called handle=0x%08X applet_attributes=0x%08X", cmd_buff[5], applet_attributes);

+

+ // TODO(Subv): An application is considered "registered" if it has already called APT::Enable

+ // handle this properly once we implement multiprocess support.

+ cmd_buff[2] = 0; // Set to not registered by default

+

+ if (app_id == static_cast<u32>(AppletId::AnyLibraryApplet)) {

+ cmd_buff[2] = HLE::Applets::IsLibraryAppletRunning() ? 1 : 0;

+ } else if (auto applet = HLE::Applets::Applet::Get(static_cast<AppletId>(app_id))) {

+ }

+ auto applet = HLE::Applets::Applet::Get(applet_id);

+ if (applet) {

+ LOG_WARNING(Service_APT, "applet has already been started id=%08X", applet_id);

+ cmd_buff[1] = RESULT_SUCCESS.raw;

+ } else {

+ cmd_buff[1] = HLE::Applets::Applet::Create(applet_id).raw;

+ }

+ LOG_DEBUG(Service_APT, "called applet_id=%08X", applet_id);

+}

+

+void PreloadLibraryApplet(Service::Interface* self) {

+ u32* cmd_buff = Kernel::GetCommandBuffer();

+ AppletId applet_id = static_cast<AppletId>(cmd_buff[1]);

+ auto applet = HLE::Applets::Applet::Get(applet_id);

+ if (applet) {

+ LOG_WARNING(Service_APT, "applet has already been started id=%08X", applet_id);

+ cmd_buff[1] = RESULT_SUCCESS.raw;

+ } else {

+ cmd_buff[1] = HLE::Applets::Applet::Create(applet_id).raw;

+ }

+ AnyLibraryApplet = 0x400,

+/**

+ * APT::GetLockHandle service function

+ * Inputs:

+ * 1 : Applet attributes

+ * Outputs:

+ * 1 : Result of function, 0 on success, otherwise error code

+ * 2 : Applet attributes

+ * 3 : Power button state

+ * 4 : IPC handle descriptor

+ * 5 : APT mutex handle

+ */

+/**

+ * APT::Enable service function

+ * Inputs:

+ * 1 : Applet attributes

+ * Outputs:

+ * 1 : Result of function, 0 on success, otherwise error code

+ */

+ * APT::PreloadLibraryApplet service function

+ * Inputs:

+ * 0 : Command header [0x00160040]

+ * 1 : Id of the applet to start

+ * Outputs:

+ * 0 : Return header

+ * 1 : Result of function, 0 on success, otherwise error code

+ */

+void PreloadLibraryApplet(Service::Interface* self);

+

+/**

+ {0x00160040, PreloadLibraryApplet, "PreloadLibraryApplet"},

+ {0x00160040, PreloadLibraryApplet, "PreloadLibraryApplet"},

+ {0x00180040, PrepareToStartLibraryApplet,"PrepareToStartLibraryApplet"},

+ {0x00160040, PreloadLibraryApplet, "PreloadLibraryApplet"},

+#include "video_core/debug_utils/debug_utils.h"

+

+ if (Pica::g_debug_context)

+ Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::BufferSwapped, nullptr);

+

+ if (params.start1 != 0) {

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)),

+ Memory::VirtualToPhysicalAddress(params.start1) >> 3);

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)),

+ Memory::VirtualToPhysicalAddress(params.end1) >> 3);

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value_32bit)), params.value1);

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].control)), params.control1);

+ }

+

+ if (params.start2 != 0) {

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)),

+ Memory::VirtualToPhysicalAddress(params.start2) >> 3);

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)),

+ Memory::VirtualToPhysicalAddress(params.end2) >> 3);

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value_32bit)), params.value2);

+ WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].control)), params.control2);

+ }

+

+ if (Pica::g_debug_context)

+ Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::GSPCommandProcessed, (void*)&command);

+const std::array<Service::HID::PadState, Settings::NativeInput::NUM_INPUTS> pad_mapping = {

+ Service::HID::PAD_A, Service::HID::PAD_B, Service::HID::PAD_X, Service::HID::PAD_Y,

+ Service::HID::PAD_L, Service::HID::PAD_R, Service::HID::PAD_ZL, Service::HID::PAD_ZR,

+ Service::HID::PAD_START, Service::HID::PAD_SELECT, Service::HID::PAD_NONE,

+ Service::HID::PAD_UP, Service::HID::PAD_DOWN, Service::HID::PAD_LEFT, Service::HID::PAD_RIGHT,

+ Service::HID::PAD_CIRCLE_UP, Service::HID::PAD_CIRCLE_DOWN, Service::HID::PAD_CIRCLE_LEFT, Service::HID::PAD_CIRCLE_RIGHT,

+ Service::HID::PAD_C_UP, Service::HID::PAD_C_DOWN, Service::HID::PAD_C_LEFT, Service::HID::PAD_C_RIGHT

+};

+

+

+#include "core/settings.h"

+

+extern const std::array<Service::HID::PadState, Settings::NativeInput::NUM_INPUTS> pad_mapping;

+

+ addrinfo hints = {};

+ addrinfo* res;

+

+ hints.ai_family = AF_INET;

+ getaddrinfo(name, NULL, &hints, &res);

+ sockaddr_in* sock_addr = reinterpret_cast<sockaddr_in*>(res->ai_addr);

+ in_addr* addr = &sock_addr->sin_addr;

+ freeaddrinfo(res);

+ u32 name_count) {

+ u32 name_count) {

+

+ if (Pica::g_debug_context)

+ Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer, nullptr);

+

+#include "core/hw/y2r.h"

+ *pos = static_cast<u32>(addr - in_addr);

+ if (extension == ".elf" || extension == ".axf")

+

+ if (extension == ".cci" || extension == ".3ds")

+

+ if (extension == ".cxi")

+ return FileType::CXI;

+

+ if (extension == ".3dsx")

+

+#include <array>

+namespace NativeInput {

+enum Values {

+ A, B, X, Y,

+ L, R, ZL, ZR,

+ START, SELECT, HOME,

+ DUP, DDOWN, DLEFT, DRIGHT,

+ SUP, SDOWN, SLEFT, SRIGHT,

+ CUP, CDOWN, CLEFT, CRIGHT,

+ NUM_INPUTS

+};

+static const std::array<const char*, NUM_INPUTS> Mapping = {

+ "pad_a", "pad_b", "pad_x", "pad_y",

+ "pad_l", "pad_r", "pad_zl", "pad_zr",

+ "pad_start", "pad_select", "pad_home",

+ "pad_dup", "pad_ddown", "pad_dleft", "pad_dright",

+ "pad_sup", "pad_sdown", "pad_sleft", "pad_sright",

+ "pad_cup", "pad_cdown", "pad_cleft", "pad_cright"

+};

+static const std::array<Values, NUM_INPUTS> All = {

+ A, B, X, Y,

+ L, R, ZL, ZR,

+ START, SELECT, HOME,

+ DUP, DDOWN, DLEFT, DRIGHT,

+ SUP, SDOWN, SLEFT, SRIGHT,

+ CUP, CDOWN, CLEFT, CRIGHT

+};

+}

+

+

+ std::array<int, NativeInput::NUM_INPUTS> input_mappings;

+ g_debug_context->OnEvent(DebugContext::Event::PicaCommandLoaded, reinterpret_cast<void*>(&id));

+ unsigned index = static_cast<unsigned>(id - PICA_REG_INDEX(command_buffer.trigger[0]));

+#if PICA_LOG_TEV

+#endif

+#if PICA_DUMP_GEOMETRY

+#endif

+ PrimitiveAssembler<VertexShader::OutputVertex> primitive_assembler(regs.triangle_topology.Value());

+#if PICA_DUMP_GEOMETRY

+#endif

+#if PICA_DUMP_GEOMETRY

+#endif

+ g_debug_context->OnEvent(DebugContext::Event::PicaCommandProcessed, reinterpret_cast<void*>(&id));

+ int num_vertices = (int)vertices.size();

+ dvle.output_register_table_size = static_cast<uint32_t>(output_info_table.size());

+ QueueForWriting((u8*)output_info_table.data(), static_cast<u32>(output_info_table.size() * sizeof(OutputRegisterInfo)));

+ ret.r() = static_cast<int>(differential.r);

+ ret.g() = static_cast<int>(differential.g);

+ ret.b() = static_cast<int>(differential.b);

+ ret.r() += static_cast<int>(differential.dr);

+ ret.g() += static_cast<int>(differential.dg);

+ ret.b() += static_cast<int>(differential.db);

+ ret.r() = Color::Convert4To8(static_cast<u8>(separate.r1));

+ ret.g() = Color::Convert4To8(static_cast<u8>(separate.g1));

+ ret.b() = Color::Convert4To8(static_cast<u8>(separate.b1));

+ ret.r() = Color::Convert4To8(static_cast<u8>(separate.r2));

+ ret.g() = Color::Convert4To8(static_cast<u8>(separate.g2));

+ ret.b() = Color::Convert4To8(static_cast<u8>(separate.b2));

+ unsigned table_index = static_cast<int>((x < 2) ? table_index_1.Value() : table_index_2.Value());

+ PicaCommandLoaded = FirstEvent,

+ PicaCommandProcessed,

+ IncomingDisplayTransfer,

+ GSPCommandProcessed,

+ BufferSwapped,

+#define PICA_DUMP_GEOMETRY 0

+#define PICA_DUMP_SHADERS 0

+#define PICA_DUMP_TEXTURES 0

+#define PICA_LOG_TEV 0

+

+#include <cstring>

+#include <unordered_map>

+std::string Regs::GetCommandName(int index) {

+ static std::unordered_map<u32, std::string> map;

+

+ if (map.empty()) {

+ #define ADD_FIELD(name) \

+ map.insert({static_cast<u32>(PICA_REG_INDEX(name)), #name}); \

+ /* TODO: change to Regs::name when VS2015 and other compilers support it */ \

+ for (u32 i = PICA_REG_INDEX(name) + 1; i < PICA_REG_INDEX(name) + sizeof(Regs().name) / 4; ++i) \

+ map.insert({i, #name + std::string("+") + std::to_string(i-PICA_REG_INDEX(name))}); \

+

+ ADD_FIELD(trigger_irq);

+ ADD_FIELD(cull_mode);

+ ADD_FIELD(viewport_size_x);

+ ADD_FIELD(viewport_size_y);

+ ADD_FIELD(viewport_depth_range);

+ ADD_FIELD(viewport_depth_far_plane);

+ ADD_FIELD(viewport_corner);

+ ADD_FIELD(texture0_enable);

+ ADD_FIELD(texture0);

+ ADD_FIELD(texture0_format);

+ ADD_FIELD(texture1);

+ ADD_FIELD(texture1_format);

+ ADD_FIELD(texture2);

+ ADD_FIELD(texture2_format);

+ ADD_FIELD(tev_stage0);

+ ADD_FIELD(tev_stage1);

+ ADD_FIELD(tev_stage2);

+ ADD_FIELD(tev_stage3);

+ ADD_FIELD(tev_combiner_buffer_input);

+ ADD_FIELD(tev_stage4);

+ ADD_FIELD(tev_stage5);

+ ADD_FIELD(tev_combiner_buffer_color);

+ ADD_FIELD(output_merger);

+ ADD_FIELD(framebuffer);

+ ADD_FIELD(vertex_attributes);

+ ADD_FIELD(index_array);

+ ADD_FIELD(num_vertices);

+ ADD_FIELD(trigger_draw);

+ ADD_FIELD(trigger_draw_indexed);

+ ADD_FIELD(vs_default_attributes_setup);

+ ADD_FIELD(command_buffer);

+ ADD_FIELD(triangle_topology);

+ ADD_FIELD(gs.bool_uniforms);

+ ADD_FIELD(gs.int_uniforms);

+ ADD_FIELD(gs.main_offset);

+ ADD_FIELD(gs.input_register_map);

+ ADD_FIELD(gs.uniform_setup);

+ ADD_FIELD(gs.program);

+ ADD_FIELD(gs.swizzle_patterns);

+ ADD_FIELD(vs.bool_uniforms);

+ ADD_FIELD(vs.int_uniforms);

+ ADD_FIELD(vs.main_offset);

+ ADD_FIELD(vs.input_register_map);

+ ADD_FIELD(vs.uniform_setup);

+ ADD_FIELD(vs.program);

+ ADD_FIELD(vs.swizzle_patterns);

+

+#undef ADD_FIELD

+ }

+

+ // Return empty string if no match is found

+ auto it = map.find(index);

+ if (it != map.end()) {

+ return it->second;

+ } else {

+ return std::string();

+ }

+}

+