1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
|
using ARMeilleure.Memory;
using Ryujinx.Cpu.LightningJit.CodeGen.Arm64;
using System;
using System.Collections.Generic;
namespace Ryujinx.Cpu.LightningJit.Arm32
{
class CodeGenContext
{
public CodeWriter CodeWriter { get; }
public Assembler Arm64Assembler { get; }
public RegisterAllocator RegisterAllocator { get; }
public MemoryManagerType MemoryManagerType { get; }
private uint _instructionAddress;
public bool IsThumb { get; }
public uint Pc { get; private set; }
public bool InITBlock { get; private set; }
private InstInfo _nextInstruction;
private bool _skipNextInstruction;
private readonly ArmCondition[] _itConditions;
private int _itCount;
private readonly List<PendingBranch> _pendingBranches;
private bool _nzcvModified;
public CodeGenContext(CodeWriter codeWriter, Assembler arm64Assembler, RegisterAllocator registerAllocator, MemoryManagerType mmType, bool isThumb)
{
CodeWriter = codeWriter;
Arm64Assembler = arm64Assembler;
RegisterAllocator = registerAllocator;
MemoryManagerType = mmType;
_itConditions = new ArmCondition[4];
_pendingBranches = new();
IsThumb = isThumb;
}
public void SetPc(uint address)
{
// Due to historical reasons, the PC value is always 2 instructions ahead on 32-bit Arm CPUs.
Pc = address + (IsThumb ? 4u : 8u);
_instructionAddress = address;
}
public void SetNextInstruction(InstInfo info)
{
_nextInstruction = info;
}
public InstInfo PeekNextInstruction()
{
return _nextInstruction;
}
public void SetSkipNextInstruction()
{
_skipNextInstruction = true;
}
public bool ConsumeSkipNextInstruction()
{
bool skip = _skipNextInstruction;
_skipNextInstruction = false;
return skip;
}
public void AddPendingBranch(InstName name, int offset)
{
_pendingBranches.Add(new(BranchType.Branch, Pc + (uint)offset, 0u, name, CodeWriter.InstructionPointer));
}
public void AddPendingCall(uint targetAddress, uint nextAddress)
{
_pendingBranches.Add(new(BranchType.Call, targetAddress, nextAddress, InstName.BlI, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(1);
RegisterAllocator.MarkGprAsUsed(RegisterUtils.LrRegister);
}
public void AddPendingIndirectBranch(InstName name, uint targetRegister)
{
_pendingBranches.Add(new(BranchType.IndirectBranch, targetRegister, 0u, name, CodeWriter.InstructionPointer));
RegisterAllocator.MarkGprAsUsed((int)targetRegister);
}
public void AddPendingTableBranch(uint rn, uint rm, bool halfword)
{
_pendingBranches.Add(new(halfword ? BranchType.TableBranchHalfword : BranchType.TableBranchByte, rn, rm, InstName.Tbb, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(2);
RegisterAllocator.MarkGprAsUsed((int)rn);
RegisterAllocator.MarkGprAsUsed((int)rm);
}
public void AddPendingIndirectCall(uint targetRegister, uint nextAddress)
{
_pendingBranches.Add(new(BranchType.IndirectCall, targetRegister, nextAddress, InstName.BlxR, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(targetRegister == RegisterUtils.LrRegister ? 1 : 0);
RegisterAllocator.MarkGprAsUsed((int)targetRegister);
RegisterAllocator.MarkGprAsUsed(RegisterUtils.LrRegister);
}
public void AddPendingSyncPoint()
{
_pendingBranches.Add(new(BranchType.SyncPoint, 0, 0, default, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(1);
}
public void AddPendingBkpt(uint imm)
{
_pendingBranches.Add(new(BranchType.SoftwareInterrupt, imm, _instructionAddress, InstName.Bkpt, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(1);
}
public void AddPendingSvc(uint imm)
{
_pendingBranches.Add(new(BranchType.SoftwareInterrupt, imm, _instructionAddress, InstName.Svc, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(1);
}
public void AddPendingUdf(uint imm)
{
_pendingBranches.Add(new(BranchType.SoftwareInterrupt, imm, _instructionAddress, InstName.Udf, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(1);
}
public void AddPendingReadCntpct(uint rt, uint rt2)
{
_pendingBranches.Add(new(BranchType.ReadCntpct, rt, rt2, InstName.Mrrc, CodeWriter.InstructionPointer));
RegisterAllocator.EnsureTempGprRegisters(1);
}
public IEnumerable<PendingBranch> GetPendingBranches()
{
return _pendingBranches;
}
public void SetItBlockStart(ReadOnlySpan<ArmCondition> conditions)
{
_itCount = conditions.Length;
for (int index = 0; index < conditions.Length; index++)
{
_itConditions[index] = conditions[index];
}
InITBlock = true;
}
public bool ConsumeItCondition(out ArmCondition condition)
{
if (_itCount != 0)
{
condition = _itConditions[--_itCount];
return true;
}
condition = ArmCondition.Al;
return false;
}
public void UpdateItState()
{
if (_itCount == 0)
{
InITBlock = false;
}
}
public void SetNzcvModified()
{
_nzcvModified = true;
}
public bool ConsumeNzcvModified()
{
bool modified = _nzcvModified;
_nzcvModified = false;
return modified;
}
}
}
|