blob: dcd06aa013ea9926afac5b9978780368705ba05c (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
|
using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCode32MsrReg : OpCode32
{
public bool R { get; }
public int Mask { get; }
public int Rd { get; }
public bool Banked { get; }
public int Rn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode);
public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
R = ((opCode >> 22) & 1) != 0;
Mask = (opCode >> 16) & 0xf;
Rd = (opCode >> 12) & 0xf;
Banked = ((opCode >> 9) & 1) != 0;
Rn = (opCode >> 0) & 0xf;
if (Rn == RegisterAlias.Aarch32Pc || Mask == 0)
{
Instruction = InstDescriptor.Undefined;
}
}
}
}
|