From a731ab3a2aad56e6ceb8b4e2444a61353246295c Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Thu, 8 Aug 2019 15:56:22 -0300
Subject: Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
---
Ryujinx.HLE/HOS/Kernel/Threading/KThread.cs | 64 +++++++++++++++++++++--------
1 file changed, 47 insertions(+), 17 deletions(-)
(limited to 'Ryujinx.HLE/HOS/Kernel/Threading/KThread.cs')
diff --git a/Ryujinx.HLE/HOS/Kernel/Threading/KThread.cs b/Ryujinx.HLE/HOS/Kernel/Threading/KThread.cs
index 50c71ea9..54d5d06c 100644
--- a/Ryujinx.HLE/HOS/Kernel/Threading/KThread.cs
+++ b/Ryujinx.HLE/HOS/Kernel/Threading/KThread.cs
@@ -1,5 +1,5 @@
-using ChocolArm64;
-using ChocolArm64.Memory;
+using ARMeilleure.Memory;
+using ARMeilleure.State;
using Ryujinx.Common.Logging;
using Ryujinx.HLE.HOS.Kernel.Common;
using Ryujinx.HLE.HOS.Kernel.Process;
@@ -7,12 +7,17 @@ using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
+using System.Threading;
namespace Ryujinx.HLE.HOS.Kernel.Threading
{
class KThread : KSynchronizationObject, IKFutureSchedulerObject
{
- public CpuThread Context { get; private set; }
+ private int _hostThreadRunning;
+
+ public Thread HostThread { get; private set; }
+
+ public IExecutionContext Context { get; private set; }
public long AffinityMask { get; set; }
@@ -152,30 +157,35 @@ namespace Ryujinx.HLE.HOS.Kernel.Threading
is64Bits = true;
}
- Context = new CpuThread(owner.Translator, owner.CpuMemory, (long)entrypoint);
+ HostThread = new Thread(() => ThreadStart(entrypoint));
- bool isAarch32 = (Owner.MmuFlags & 1) == 0;
+ if (System.UseLegacyJit)
+ {
+ Context = new ChocolArm64.State.CpuThreadState();
+ }
+ else
+ {
+ Context = new ARMeilleure.State.ExecutionContext();
+ }
- Context.ThreadState.Aarch32 = isAarch32;
+ bool isAarch32 = (Owner.MmuFlags & 1) == 0;
- Context.ThreadState.X0 = argsPtr;
+ Context.SetX(0, argsPtr);
if (isAarch32)
{
- Context.ThreadState.X13 = (uint)stackTop;
+ Context.SetX(13, (uint)stackTop);
}
else
{
- Context.ThreadState.X31 = stackTop;
+ Context.SetX(31, stackTop);
}
- Context.ThreadState.CntfrqEl0 = 19200000;
- Context.ThreadState.Tpidr = (long)_tlsAddress;
+ Context.CntfrqEl0 = 19200000;
+ Context.Tpidr = (long)_tlsAddress;
owner.SubscribeThreadEventHandlers(Context);
- Context.WorkFinished += ThreadFinishedHandler;
-
ThreadUid = System.GetThreadUid();
_hasBeenInitialized = true;
@@ -1002,8 +1012,8 @@ namespace Ryujinx.HLE.HOS.Kernel.Threading
public void SetEntryArguments(long argsPtr, int threadHandle)
{
- Context.ThreadState.X0 = (ulong)argsPtr;
- Context.ThreadState.X1 = (ulong)threadHandle;
+ Context.SetX(0, (ulong)argsPtr);
+ Context.SetX(1, (ulong)threadHandle);
}
public void TimeUp()
@@ -1013,7 +1023,7 @@ namespace Ryujinx.HLE.HOS.Kernel.Threading
public string GetGuestStackTrace()
{
- return Owner.Debugger.GetGuestStackTrace(Context.ThreadState);
+ return Owner.Debugger.GetGuestStackTrace(Context);
}
public void PrintGuestStackTrace()
@@ -1026,12 +1036,32 @@ namespace Ryujinx.HLE.HOS.Kernel.Threading
Logger.PrintInfo(LogClass.Cpu, trace.ToString());
}
- private void ThreadFinishedHandler(object sender, EventArgs e)
+ public void Execute()
+ {
+ if (Interlocked.CompareExchange(ref _hostThreadRunning, 1, 0) == 0)
+ {
+ HostThread.Start();
+ }
+ }
+
+ private void ThreadStart(ulong entrypoint)
+ {
+ Owner.Translator.Execute(Context, entrypoint);
+
+ ThreadExit();
+ }
+
+ private void ThreadExit()
{
System.Scheduler.ExitThread(this);
System.Scheduler.RemoveThread(this);
}
+ public bool IsCurrentHostThread()
+ {
+ return Thread.CurrentThread == HostThread;
+ }
+
public override bool IsSignaled()
{
return _hasExited;
--
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