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AgeCommit message (Expand)Author
2022-08-18Removed unused usings. (#3593)1.1.223Nicholas Rodine
2022-08-05Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)1.1.208gdkchan
2022-07-06Implement CPU FCVT Half <-> Double conversion variants (#3439)1.1.165gdkchan
2022-05-31Refactor CPU interface to allow the implementation of other CPU emulators (#3...1.1.134gdkchan
2022-05-02Support memory aliasing (#2954)1.1.110gdkchan
2022-04-21T32: Implement load/store single (immediate) (#3186)1.1.106merry
2022-03-11KThread: Fix GetPsr mask (#3180)1.1.65merry
2022-03-06T32: Implement Data Processing (Modified Immediate) instructions (#3178)1.1.63merry
2022-03-05A32: Fix ALU immediate instructions (#3179)1.1.60merry
2022-03-04T32: Implement B, B.cond, BL, BLX (#3155)1.1.57merry
2022-02-22T32: Implement ALU (shifted register) instructions (#3135)1.1.53merry
2022-02-17ARMeilleure: Thumb support (All T16 instructions) (#3105)1.1.36merry
2022-02-08ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)1.1.21merry
2022-02-06ARMeilleure: A32: Implement SHADD8 (#3086)1.1.18merry
2022-01-19Implement FCVTNS (Scalar GP) (#2953)sharmander
2022-01-04CPU - Implement FCVTMS (Vector) (#2937)sharmander
2021-12-08Implement UHADD8 instruction (#2908)Piyachet Kanda
2021-06-23Implement VORN (register) Arm32 instruction (#2396)gdkchan
2021-05-29Add multi-level function table (#2228)FICTURE7
2021-05-24POWER - Performance Optimizations With Extensive Ramifications (#2286)riperiperi
2021-03-25Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)LDj3SNuD
2021-02-22Implement VCNT instruction (#1963)mageven
2021-01-20CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests...LDj3SNuD
2021-01-04CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian...LDj3SNuD
2020-12-17Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow...LDj3SNuD
2020-12-16CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)sharmander
2020-12-15CPU: Implement VFMA (Vector) (#1762)sharmander
2020-12-07CPU: Implement VFNMA.F32 | F.64 (#1783)sharmander
2020-12-07Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (...LDj3SNuD
2020-12-03CPU: Implement VFNMS.F32/64 (#1758)sharmander
2020-11-18CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & F...LDj3SNuD
2020-11-17shader cache: Fix Linux boot issues (#1709)Mary
2020-08-31CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)LDj3SNuD
2020-08-13Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)LDj3SNuD
2020-08-08CPU: This PR fixes Fpscr, among other things. (#1433)LDj3SNuD
2020-07-19Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)Valentin PONS
2020-07-17CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394)LDj3SNuD
2020-07-17CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)LDj3SNuD
2020-07-13Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)LDj3SNuD
2020-07-13Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli vari...riperiperi
2020-06-24Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)riperiperi
2020-06-16Add Profiled Persistent Translation Cache. (#769)LDj3SNuD
2020-05-27Add FMaxNmV & FMinNmV Inst.s with Test. (#1279)LDj3SNuD
2020-05-04Implement a new physical memory manager and replace DeviceMemory (#856)gdkchan
2020-04-17Improve V128 (#1097)Ficture Seven
2020-03-24Add Fcvtas_S/V & Fcvtau_S/V. (#1018)LDj3SNuD
2020-03-14Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)riperiperi
2020-03-11Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other...gdkchan
2020-03-10Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)gdkchan
2020-03-01Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)gdkchan
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