| Age | Commit message (Expand) | Author |
|---|
| 2021-01-04 | CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian... | LDj3SNuD |
| 2020-07-13 | Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) | LDj3SNuD |
| 2020-03-01 | Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956) | gdkchan |
| 2019-08-08 | Add a new JIT compiler for CPU code (#693) | gdkchan |
| 2019-06-29 | Implement the remaining tests for Simd and Fp instructions of data processing... | LDj3SNuD |
| 2019-03-13 | Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. ... | LDj3SNuD |
| 2018-12-26 | Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl.... | LDj3SNuD |
| 2018-12-01 | Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516) | LDj3SNuD |
| 2018-11-18 | Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V... | LDj3SNuD |
| 2018-11-01 | Add Flush-to-zero mode (input, output) to FP instructions (slow paths); updat... | LDj3SNuD |
| 2018-10-30 | Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) | Alex Barney |
| 2018-10-28 | Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 ... | LDj3SNuD |
| 2018-10-13 | Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_... | LDj3SNuD |
| 2018-10-05 | Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437) | LDj3SNuD |
| 2018-09-17 | Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; a... | LDj3SNuD |
| 2018-09-08 | Remove old Tester, update Tests (some reworks). (#400) | LDj3SNuD |
| 2018-09-01 | Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_... | LDj3SNuD |
| 2018-09-01 | Ryujinx.Tests: Add unicorn to test framework (#389) | Merry |
| 2018-08-27 | Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380) | LDj3SNuD |
| 2018-08-16 | Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed... | LDj3SNuD |
| 2018-08-10 | Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. N... | LDj3SNuD |
| 2018-08-04 | Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector)... | LDj3SNuD |
| 2018-07-18 | Implement Ssubw_V and Usubw_V instructions. (#287) | LDj3SNuD |
| 2018-07-15 | Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& P... | LDj3SNuD |
| 2018-07-03 | Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Impr... | LDj3SNuD |
| 2018-06-30 | Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V... | LDj3SNuD |
| 2018-06-18 | Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmts... | LDj3SNuD |
| 2018-05-11 | Add intrinsics support (#121) | gdkchan |
| 2018-04-29 | Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110) | LDj3SNuD |
| 2018-04-25 | Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_... | LDj3SNuD |
| 2018-04-21 | Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. ... | LDj3SNuD |
| 2018-04-20 | Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tes... | LDj3SNuD |
