| Age | Commit message (Expand) | Author |
|---|
| 2021-05-24 | POWER - Performance Optimizations With Extensive Ramifications (#2286) | riperiperi |
| 2021-05-24 | Improve accuracy of reciprocal step instructions (#2305) | gdkchan |
| 2021-05-20 | Use branch instead of tailcall for recursive calls (#2282) | FICTURE7 |
| 2021-05-20 | Add `BIC/ORR Vd.T, #imm` fast path (#2279) | FICTURE7 |
| 2021-05-17 | Allow `LocalVariable` to be assigned more than once (#2288) | FICTURE7 |
| 2021-05-13 | Fold constant offsets and group constant addresses (#2285) | gdkchan |
| 2021-05-13 | PPTC meets ExeFS Patching. (#1865) | LDj3SNuD |
| 2021-04-18 | Add inlined on translation call counting (#2190) | FICTURE7 |
| 2021-04-13 | PPTC vs. giant ExeFS. (#2168) | LDj3SNuD |
| 2021-04-07 | (CPU) Fix CRC32 instruction when constant values are used as input (#2183) | gdkchan |
| 2021-04-02 | Improve `StoreToContext` emission (#2155) | FICTURE7 |
| 2021-04-02 | Reduce allocation during SSA construction (#2162) | FICTURE7 |
| 2021-03-25 | Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139) | LDj3SNuD |
| 2021-03-22 | Fix inconsistencies in progress reporting (#2129) | mageven |
| 2021-03-03 | Add progress reporting to PTC and Shader Cache (#2057) | mageven |
| 2021-02-23 | PPTC: Fix unwanted propagation of a relocatable constant in a specific case. ... | LDj3SNuD |
| 2021-02-22 | Implement VCNT instruction (#1963) | mageven |
| 2021-02-22 | PPTC & Pool Enhancements. (#1968) | LDj3SNuD |
| 2021-02-21 | Turn Copy into Fill in HybridAllocator (#2010) | FICTURE7 |
| 2021-02-17 | Fix memory tracking performance regression (#2026) | gdkchan |
| 2021-02-16 | Validate CPU virtual addresses on access (#1987) | gdkchan |
| 2021-02-08 | Optimization | Modify Add (Integer) Instruction to use LEA instead. (#1971) | sharmander |
| 2021-02-08 | Disable partial JIT invalidation on unmap (#1991) | gdkchan |
| 2021-01-28 | Lower precision of estimate instruction results to match Arm behavior (#1943) | gdkchan |
| 2021-01-26 | Implement PRFM (register variant) as NOP (#1956) | mageven |
| 2021-01-25 | Add VCLZ.* fast path (#1917) | FICTURE7 |
| 2021-01-20 | CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests... | LDj3SNuD |
| 2021-01-12 | Add a simple Pools Limiter. (#1830) | LDj3SNuD |
| 2021-01-04 | CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian... | LDj3SNuD |
| 2020-12-24 | Hotfix for #1814 | Ac_K |
| 2020-12-24 | Free up memory allocated by Pools during any PPTC translations at boot time. ... | LDj3SNuD |
| 2020-12-17 | Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow... | LDj3SNuD |
| 2020-12-17 | PPTC Follow-up. (#1712) | LDj3SNuD |
| 2020-12-16 | CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776) | sharmander |
| 2020-12-16 | Clear JIT cache on exit (#1518) | gdkchan |
| 2020-12-15 | CPU: Implement VFMA (Vector) (#1762) | sharmander |
| 2020-12-14 | Fix pre-allocator shift instruction copy on a specific case (#1752) | gdkchan |
| 2020-12-13 | Fix register read after write on STREX implementation (#1801) | gdkchan |
| 2020-12-07 | CPU: Implement VFNMA.F32 | F.64 (#1783) | sharmander |
| 2020-12-07 | Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (... | LDj3SNuD |
| 2020-12-03 | CPU: Implement VFNMS.F32/64 (#1758) | sharmander |
| 2020-12-02 | IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special h... | gdkchan |
| 2020-11-20 | Use backup when PTC compression is corrupt (#1704) | riperiperi |
| 2020-11-18 | CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & F... | LDj3SNuD |
| 2020-11-17 | shader cache: Fix Linux boot issues (#1709) | Mary |
| 2020-11-15 | infra: Migrate to .NET 5 (#1694) | Mary |
| 2020-11-04 | Fix LiveInterval.Split (#1660) | FICTURE7 |
| 2020-10-21 | Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626) | gdkchan |
| 2020-10-16 | Memory Read/Write Tracking using Region Handles (#1272) | riperiperi |
| 2020-10-13 | Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths... | LDj3SNuD |
