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Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs')
-rw-r--r--src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs51
1 files changed, 32 insertions, 19 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
index e7fad89f..f81d22c2 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
@@ -10,30 +10,41 @@ namespace Ryujinx.Tests.Cpu
{
#if SimdShImm32
-#region "ValueSource (Types)"
+ #region "ValueSource (Types)"
private static ulong[] _1D_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _2S_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[]
+ {
+ 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _4H_()
{
- return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[]
+ {
+ 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[]
+ {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
-#endregion
+ #endregion
-#region "ValueSource (Opcodes)"
+ #region "ValueSource (Opcodes)"
private static uint[] _Vshr_Imm_SU8_()
{
return new[]
@@ -41,7 +52,7 @@ namespace Ryujinx.Tests.Cpu
0xf2880010u, // VSHR.S8 D0, D0, #8
0xf2880110u, // VSRA.S8 D0, D0, #8
0xf2880210u, // VRSHR.S8 D0, D0, #8
- 0xf2880310u // VRSRA.S8 D0, D0, #8
+ 0xf2880310u, // VRSRA.S8 D0, D0, #8
};
}
@@ -52,7 +63,7 @@ namespace Ryujinx.Tests.Cpu
0xf2900010u, // VSHR.S16 D0, D0, #16
0xf2900110u, // VSRA.S16 D0, D0, #16
0xf2900210u, // VRSHR.S16 D0, D0, #16
- 0xf2900310u // VRSRA.S16 D0, D0, #16
+ 0xf2900310u, // VRSRA.S16 D0, D0, #16
};
}
@@ -63,7 +74,7 @@ namespace Ryujinx.Tests.Cpu
0xf2a00010u, // VSHR.S32 D0, D0, #32
0xf2a00110u, // VSRA.S32 D0, D0, #32
0xf2a00210u, // VRSHR.S32 D0, D0, #32
- 0xf2a00310u // VRSRA.S32 D0, D0, #32
+ 0xf2a00310u, // VRSRA.S32 D0, D0, #32
};
}
@@ -73,7 +84,7 @@ namespace Ryujinx.Tests.Cpu
{
0xf2800190u, // VSRA.S64 D0, D0, #64
0xf2800290u, // VRSHR.S64 D0, D0, #64
- 0xf2800090u // VSHR.S64 D0, D0, #64
+ 0xf2800090u, // VSHR.S64 D0, D0, #64
};
}
@@ -83,7 +94,7 @@ namespace Ryujinx.Tests.Cpu
{
0xf2800910u, // VORR.I16 D0, #0 (immediate value changes it into QSHRN)
0xf2800950u, // VORR.I16 Q0, #0 (immediate value changes it into QRSHRN)
- 0xf2800850u // VMOV.I16 Q0, #0 (immediate value changes it into RSHRN)
+ 0xf2800850u, // VMOV.I16 Q0, #0 (immediate value changes it into RSHRN)
};
}
@@ -92,10 +103,10 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0xf3800810u, // VMOV.I16 D0, #0x80 (immediate value changes it into QSHRUN)
- 0xf3800850u // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN)
+ 0xf3800850u, // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN)
};
}
-#endregion
+ #endregion
private const int RndCnt = 2;
private const int RndCntShiftImm = 2;
@@ -171,12 +182,14 @@ namespace Ryujinx.Tests.Cpu
{
opcode |= 1 << 6;
- rd >>= 1; rd <<= 1;
- rm >>= 1; rm <<= 1;
+ rd >>= 1;
+ rd <<= 1;
+ rm >>= 1;
+ rm <<= 1;
}
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
- opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
+ opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= (imm6 & 0x3f) << 16;
@@ -312,4 +325,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-} \ No newline at end of file
+}