diff options
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 180 |
1 files changed, 102 insertions, 78 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 603e2a55..1db90bfa 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu { #if SimdReg32 -#region "ValueSource (Opcodes)" + #region "ValueSource (Opcodes)" private static uint[] _V_Add_Sub_Long_Wide_I_() { return new[] @@ -20,7 +20,7 @@ namespace Ryujinx.Tests.Cpu 0xf2800000u, // VADDL.S8 Q0, D0, D0 0xf2800100u, // VADDW.S8 Q0, Q0, D0 0xf2800200u, // VSUBL.S8 Q0, D0, D0 - 0xf2800300u // VSUBW.S8 Q0, Q0, D0 + 0xf2800300u, // VSUBW.S8 Q0, Q0, D0 }; } @@ -31,7 +31,7 @@ namespace Ryujinx.Tests.Cpu 0xEEA00A00u, // VFMA. F32 S0, S0, S0 0xEEA00A40u, // VFMS. F32 S0, S0, S0 0xEE900A40u, // VFNMA.F32 S0, S0, S0 - 0xEE900A00u // VFNMS.F32 S0, S0, S0 + 0xEE900A00u, // VFNMS.F32 S0, S0, S0 }; } @@ -42,7 +42,7 @@ namespace Ryujinx.Tests.Cpu 0xEEA00B00u, // VFMA. F64 D0, D0, D0 0xEEA00B40u, // VFMS. F64 D0, D0, D0 0xEE900B40u, // VFNMA.F64 D0, D0, D0 - 0xEE900B00u // VFNMS.F64 D0, D0, D0 + 0xEE900B00u, // VFNMS.F64 D0, D0, D0 }; } @@ -51,7 +51,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0xF2000C10u, // VFMA.F32 D0, D0, D0 - 0xF2200C10u // VFMS.F32 D0, D0, D0 + 0xF2200C10u, // VFMS.F32 D0, D0, D0 }; } @@ -62,7 +62,7 @@ namespace Ryujinx.Tests.Cpu 0xEE000A00u, // VMLA. F32 S0, S0, S0 0xEE000A40u, // VMLS. F32 S0, S0, S0 0xEE100A40u, // VNMLA.F32 S0, S0, S0 - 0xEE100A00u // VNMLS.F32 S0, S0, S0 + 0xEE100A00u, // VNMLS.F32 S0, S0, S0 }; } @@ -73,7 +73,7 @@ namespace Ryujinx.Tests.Cpu 0xEE000B00u, // VMLA. F64 D0, D0, D0 0xEE000B40u, // VMLS. F64 D0, D0, D0 0xEE100B40u, // VNMLA.F64 D0, D0, D0 - 0xEE100B00u // VNMLS.F64 D0, D0, D0 + 0xEE100B00u, // VNMLS.F64 D0, D0, D0 }; } @@ -82,7 +82,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0xf2800800u, // VMLAL.S8 Q0, D0, D0 - 0xf2800a00u // VMLSL.S8 Q0, D0, D0 + 0xf2800a00u, // VMLSL.S8 Q0, D0, D0 }; } @@ -92,7 +92,7 @@ namespace Ryujinx.Tests.Cpu { 0xf3000d00u, // VPADD.F32 D0, D0, D0 0xf3000f00u, // VPMAX.F32 D0, D0, D0 - 0xf3200f00u // VPMIN.F32 D0, D0, D0 + 0xf3200f00u, // VPMIN.F32 D0, D0, D0 }; } @@ -100,7 +100,7 @@ namespace Ryujinx.Tests.Cpu { return new[] { - 0xf2000b10u // VPADD.I8 D0, D0, D0 + 0xf2000b10u, // VPADD.I8 D0, D0, D0 }; } @@ -119,26 +119,30 @@ namespace Ryujinx.Tests.Cpu return new[] { 0xf2000050u, // VQADD.S8 Q0, Q0, Q0 - 0xf2000250u // VQSUB.S8 Q0, Q0, Q0 + 0xf2000250u, // VQSUB.S8 Q0, Q0, Q0 }; } -#endregion + #endregion -#region "ValueSource (Types)" + #region "ValueSource (Types)" private static ulong[] _8B1D_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _8B4H2S1D_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static IEnumerable<ulong> _1S_F_() @@ -152,19 +156,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x00000000007FFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x0000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0x00000000FF800000ul; // -Infinity yield return 0x000000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload) @@ -194,19 +198,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x007FFFFF007FFFFFul; // +Max Subnormal yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFF800000FF800000ul; // -Infinity yield return 0x7F8000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload) @@ -235,19 +239,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000000000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFFF0000000000000ul; // -Infinity yield return 0x7FF0000000000000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN) yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload) @@ -264,13 +268,13 @@ namespace Ryujinx.Tests.Cpu yield return rnd2; } } -#endregion + #endregion private const int RndCnt = 2; - private static readonly bool NoZeros = false; - private static readonly bool NoInfs = false; - private static readonly bool NoNaNs = false; + private static readonly bool _noZeros = false; + private static readonly bool _noInfs = false; + private static readonly bool _noNaNs = false; [Test, Pairwise, Description("SHA256H.32 <Qd>, <Qn>, <Qm>")] public void Sha256h_V([Values(0xF3000C40u)] uint opcode, @@ -288,7 +292,7 @@ namespace Ryujinx.Tests.Cpu { opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); V128 v0 = MakeVectorE0E1(z0, z1); V128 v1 = MakeVectorE0E1(a0, a1); @@ -322,7 +326,7 @@ namespace Ryujinx.Tests.Cpu { opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); V128 v0 = MakeVectorE0E1(z0, z1); V128 v1 = MakeVectorE0E1(a0, a1); @@ -356,7 +360,7 @@ namespace Ryujinx.Tests.Cpu { opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); V128 v0 = MakeVectorE0E1(z0, z1); V128 v1 = MakeVectorE0E1(a0, a1); @@ -396,7 +400,7 @@ namespace Ryujinx.Tests.Cpu rd <<= 1; } - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); @@ -425,12 +429,14 @@ namespace Ryujinx.Tests.Cpu opcode |= 1 << 24; } - rd >>= 1; rd <<= 1; - rn >>= 1; rn <<= 1; + rd >>= 1; + rd <<= 1; + rn >>= 1; + rn <<= 1; opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= (size & 0x3) << 20; @@ -455,12 +461,12 @@ namespace Ryujinx.Tests.Cpu if (size == 3) { - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); } else { - opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5); + opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5); opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22); } @@ -480,7 +486,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void Vfma_Vfms_Vfnma_Vfnms_S_F32([ValueSource(nameof(_Vfma_Vfms_Vfnma_Vfnms_S_F32_))] uint opcode, [Values(0u, 1u, 2u, 3u)] uint rd, [Values(0u, 1u, 2u, 3u)] uint rn, @@ -491,8 +499,8 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_1S_F_))] ulong s3) { opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11); - opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) << 15); - opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1); + opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) << 15); + opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1); V128 v0 = MakeVectorE0E1E2E3((uint)s0, (uint)s1, (uint)s2, (uint)s3); @@ -501,7 +509,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void Vfma_Vfms_Vfnma_Vfnms_S_F64([ValueSource(nameof(_Vfma_Vfms_Vfnma_Vfnms_S_F64_))] uint opcode, [Values(0u, 1u)] uint rd, [Values(0u, 1u)] uint rn, @@ -510,8 +520,8 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_1D_F_))] ulong d1) { opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12); - opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); - opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); + opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); + opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); V128 v0 = MakeVectorE0E1(d0, d1); @@ -520,7 +530,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void Vfma_Vfms_V_F32([ValueSource(nameof(_Vfma_Vfms_V_F32_))] uint opcode, [Values(0u, 1u, 2u, 3u)] uint rd, [Values(0u, 1u, 2u, 3u)] uint rn, @@ -535,14 +547,17 @@ namespace Ryujinx.Tests.Cpu { opcode |= 1 << 6; - rd >>= 1; rd <<= 1; - rn >>= 1; rn <<= 1; - rm >>= 1; rm <<= 1; + rd >>= 1; + rd <<= 1; + rn >>= 1; + rn <<= 1; + rm >>= 1; + rm <<= 1; } opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); V128 v0 = MakeVectorE0E1(d0, d1); V128 v1 = MakeVectorE0E1(d2, d3); @@ -552,7 +567,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void Vmla_Vmls_Vnmla_Vnmls_S_F32([ValueSource(nameof(_Vmla_Vmls_Vnmla_Vnmls_S_F32_))] uint opcode, [Values(0u, 1u, 2u, 3u)] uint rd, [Values(0u, 1u, 2u, 3u)] uint rn, @@ -563,8 +579,8 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_1S_F_))] ulong s3) { opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11); - opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) << 15); - opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1); + opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) << 15); + opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1); V128 v0 = MakeVectorE0E1E2E3((uint)s0, (uint)s1, (uint)s2, (uint)s3); @@ -573,7 +589,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void Vmla_Vmls_Vnmla_Vnmls_S_F64([ValueSource(nameof(_Vmla_Vmls_Vnmla_Vnmls_S_F64_))] uint opcode, [Values(0u, 1u)] uint rd, [Values(0u, 1u)] uint rn, @@ -582,8 +599,8 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_1D_F_))] ulong d1) { opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12); - opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); - opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); + opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); + opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); V128 v0 = MakeVectorE0E1(d0, d1); @@ -603,7 +620,7 @@ namespace Ryujinx.Tests.Cpu [Random(RndCnt)] ulong b, [Values] bool u) { - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); @@ -636,7 +653,7 @@ namespace Ryujinx.Tests.Cpu { uint opcode = 0xf2800c00u; // VMULL.S8 Q0, D0, D0 - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); @@ -678,11 +695,12 @@ namespace Ryujinx.Tests.Cpu uint opcode = 0xf2800e00u; // VMULL.P8 Q0, D0, D0 - rd >>= 1; rd <<= 1; + rd >>= 1; + rd <<= 1; opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12); - opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); - opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); + opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); + opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); opcode |= (size & 0x3) << 20; @@ -723,7 +741,7 @@ namespace Ryujinx.Tests.Cpu opcode |= 1 << 24; } - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); @@ -751,7 +769,7 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_2S_F_))] ulong b0, [ValueSource(nameof(_2S_F_))] ulong b1) { - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); @@ -774,7 +792,7 @@ namespace Ryujinx.Tests.Cpu [Random(RndCnt)] ulong a, [Random(RndCnt)] ulong b) { - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); @@ -805,7 +823,7 @@ namespace Ryujinx.Tests.Cpu opcode |= 1 << 24; } - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); @@ -836,13 +854,16 @@ namespace Ryujinx.Tests.Cpu opcode |= 1 << 24; } - rd >>= 1; rd <<= 1; - rn >>= 1; rn <<= 1; - rm >>= 1; rm <<= 1; + rd >>= 1; + rd <<= 1; + rn >>= 1; + rn <<= 1; + rm >>= 1; + rm <<= 1; opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= (size & 0x3) << 20; @@ -864,15 +885,18 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_8B4H2S1D_))] ulong b, [Values(1u, 2u)] uint size) // <S16, S32> { - rd >>= 1; rd <<= 1; - rn >>= 1; rn <<= 1; - rm >>= 1; rm <<= 1; + rd >>= 1; + rd <<= 1; + rn >>= 1; + rn <<= 1; + rm >>= 1; + rm <<= 1; uint opcode = 0xf2100b40u & ~(3u << 20); // VQDMULH.S16 Q0, Q0, Q0 opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= (size & 0x3) << 20; @@ -886,4 +910,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -}
\ No newline at end of file +} |