diff options
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 582 |
1 files changed, 315 insertions, 267 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs index 1f2a6bc8..207f7608 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs @@ -11,75 +11,93 @@ namespace Ryujinx.Tests.Cpu { #if SimdReg -#region "ValueSource (Types)" + #region "ValueSource (Types)" private static ulong[] _1B1H1S1D_() { - return new[] { 0x0000000000000000ul, 0x000000000000007Ful, - 0x0000000000000080ul, 0x00000000000000FFul, - 0x0000000000007FFFul, 0x0000000000008000ul, - 0x000000000000FFFFul, 0x000000007FFFFFFFul, - 0x0000000080000000ul, 0x00000000FFFFFFFFul, - 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul, - 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x000000000000007Ful, + 0x0000000000000080ul, 0x00000000000000FFul, + 0x0000000000007FFFul, 0x0000000000008000ul, + 0x000000000000FFFFul, 0x000000007FFFFFFFul, + 0x0000000080000000ul, 0x00000000FFFFFFFFul, + 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul, + 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _1D_() { - return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _1H1S_() { - return new[] { 0x0000000000000000ul, 0x0000000000007FFFul, - 0x0000000000008000ul, 0x000000000000FFFFul, - 0x000000007FFFFFFFul, 0x0000000080000000ul, - 0x00000000FFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x0000000000007FFFul, + 0x0000000000008000ul, 0x000000000000FFFFul, + 0x000000007FFFFFFFul, 0x0000000080000000ul, + 0x00000000FFFFFFFFul, + }; } private static ulong[] _4H2S_() { - return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _4H2S1D_() { - return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _8B_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _8B1D_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _8B4H2S_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _8B4H2S1D_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static IEnumerable<ulong> _1S_F_() @@ -93,19 +111,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x00000000007FFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x0000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0x00000000FF800000ul; // -Infinity yield return 0x000000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload) @@ -135,19 +153,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x007FFFFF007FFFFFul; // +Max Subnormal yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFF800000FF800000ul; // -Infinity yield return 0x7F8000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload) @@ -176,19 +194,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000000000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFFF0000000000000ul; // -Infinity yield return 0x7FF0000000000000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN) yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload) @@ -205,9 +223,9 @@ namespace Ryujinx.Tests.Cpu yield return rnd2; } } -#endregion + #endregion -#region "ValueSource (Opcodes)" + #region "ValueSource (Opcodes)" private static uint[] _F_Abd_Add_Div_Mul_Mulx_Nmul_Sub_S_S_() { return new[] @@ -218,7 +236,7 @@ namespace Ryujinx.Tests.Cpu 0x1E220820u, // FMUL S0, S1, S2 0x5E22DC20u, // FMULX S0, S1, S2 0x1E228820u, // FNMUL S0, S1, S2 - 0x1E223820u // FSUB S0, S1, S2 + 0x1E223820u, // FSUB S0, S1, S2 }; } @@ -232,7 +250,7 @@ namespace Ryujinx.Tests.Cpu 0x1E620820u, // FMUL D0, D1, D2 0x5E62DC20u, // FMULX D0, D1, D2 0x1E628820u, // FNMUL D0, D1, D2 - 0x1E623820u // FSUB D0, D1, D2 + 0x1E623820u, // FSUB D0, D1, D2 }; } @@ -246,7 +264,7 @@ namespace Ryujinx.Tests.Cpu 0x2E20FC00u, // FDIV V0.2S, V0.2S, V0.2S 0x2E20DC00u, // FMUL V0.2S, V0.2S, V0.2S 0x0E20DC00u, // FMULX V0.2S, V0.2S, V0.2S - 0x0EA0D400u // FSUB V0.2S, V0.2S, V0.2S + 0x0EA0D400u, // FSUB V0.2S, V0.2S, V0.2S }; } @@ -260,7 +278,7 @@ namespace Ryujinx.Tests.Cpu 0x6E60FC00u, // FDIV V0.2D, V0.2D, V0.2D 0x6E60DC00u, // FMUL V0.2D, V0.2D, V0.2D 0x4E60DC00u, // FMULX V0.2D, V0.2D, V0.2D - 0x4EE0D400u // FSUB V0.2D, V0.2D, V0.2D + 0x4EE0D400u, // FSUB V0.2D, V0.2D, V0.2D }; } @@ -272,7 +290,7 @@ namespace Ryujinx.Tests.Cpu 0x7EA2EC20u, // FACGT S0, S1, S2 0x5E22E420u, // FCMEQ S0, S1, S2 0x7E22E420u, // FCMGE S0, S1, S2 - 0x7EA2E420u // FCMGT S0, S1, S2 + 0x7EA2E420u, // FCMGT S0, S1, S2 }; } @@ -284,7 +302,7 @@ namespace Ryujinx.Tests.Cpu 0x7EE2EC20u, // FACGT D0, D1, D2 0x5E62E420u, // FCMEQ D0, D1, D2 0x7E62E420u, // FCMGE D0, D1, D2 - 0x7EE2E420u // FCMGT D0, D1, D2 + 0x7EE2E420u, // FCMGT D0, D1, D2 }; } @@ -296,7 +314,7 @@ namespace Ryujinx.Tests.Cpu 0x2EA0EC00u, // FACGT V0.2S, V0.2S, V0.2S 0x0E20E400u, // FCMEQ V0.2S, V0.2S, V0.2S 0x2E20E400u, // FCMGE V0.2S, V0.2S, V0.2S - 0x2EA0E400u // FCMGT V0.2S, V0.2S, V0.2S + 0x2EA0E400u, // FCMGT V0.2S, V0.2S, V0.2S }; } @@ -308,7 +326,7 @@ namespace Ryujinx.Tests.Cpu 0x6EE0EC00u, // FACGT V0.2D, V0.2D, V0.2D 0x4E60E400u, // FCMEQ V0.2D, V0.2D, V0.2D 0x6E60E400u, // FCMGE V0.2D, V0.2D, V0.2D - 0x6EE0E400u // FCMGT V0.2D, V0.2D, V0.2D + 0x6EE0E400u, // FCMGT V0.2D, V0.2D, V0.2D }; } @@ -317,7 +335,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x1E222020u, // FCMP S1, S2 - 0x1E222030u // FCMPE S1, S2 + 0x1E222030u, // FCMPE S1, S2 }; } @@ -326,7 +344,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x1E622020u, // FCMP D1, D2 - 0x1E622030u // FCMPE D1, D2 + 0x1E622030u, // FCMPE D1, D2 }; } @@ -337,7 +355,7 @@ namespace Ryujinx.Tests.Cpu 0x1F020C20u, // FMADD S0, S1, S2, S3 0x1F028C20u, // FMSUB S0, S1, S2, S3 0x1F220C20u, // FNMADD S0, S1, S2, S3 - 0x1F228C20u // FNMSUB S0, S1, S2, S3 + 0x1F228C20u, // FNMSUB S0, S1, S2, S3 }; } @@ -348,7 +366,7 @@ namespace Ryujinx.Tests.Cpu 0x1F420C20u, // FMADD D0, D1, D2, D3 0x1F428C20u, // FMSUB D0, D1, D2, D3 0x1F620C20u, // FNMADD D0, D1, D2, D3 - 0x1F628C20u // FNMSUB D0, D1, D2, D3 + 0x1F628C20u, // FNMSUB D0, D1, D2, D3 }; } @@ -359,7 +377,7 @@ namespace Ryujinx.Tests.Cpu 0x1E224820u, // FMAX S0, S1, S2 0x1E226820u, // FMAXNM S0, S1, S2 0x1E225820u, // FMIN S0, S1, S2 - 0x1E227820u // FMINNM S0, S1, S2 + 0x1E227820u, // FMINNM S0, S1, S2 }; } @@ -370,7 +388,7 @@ namespace Ryujinx.Tests.Cpu 0x1E624820u, // FMAX D0, D1, D2 0x1E626820u, // FMAXNM D0, D1, D2 0x1E625820u, // FMIN D0, D1, D2 - 0x1E627820u // FMINNM D0, D1, D2 + 0x1E627820u, // FMINNM D0, D1, D2 }; } @@ -385,7 +403,7 @@ namespace Ryujinx.Tests.Cpu 0x0EA0F400u, // FMIN V0.2S, V0.2S, V0.2S 0x0EA0C400u, // FMINNM V0.2S, V0.2S, V0.2S 0x2EA0C400u, // FMINNMP V0.2S, V0.2S, V0.2S - 0x2EA0F400u // FMINP V0.2S, V0.2S, V0.2S + 0x2EA0F400u, // FMINP V0.2S, V0.2S, V0.2S }; } @@ -400,7 +418,7 @@ namespace Ryujinx.Tests.Cpu 0x4EE0F400u, // FMIN V0.2D, V0.2D, V0.2D 0x4EE0C400u, // FMINNM V0.2D, V0.2D, V0.2D 0x6EE0C400u, // FMINNMP V0.2D, V0.2D, V0.2D - 0x6EE0F400u // FMINP V0.2D, V0.2D, V0.2D + 0x6EE0F400u, // FMINP V0.2D, V0.2D, V0.2D }; } @@ -409,7 +427,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x0E20CC00u, // FMLA V0.2S, V0.2S, V0.2S - 0x0EA0CC00u // FMLS V0.2S, V0.2S, V0.2S + 0x0EA0CC00u, // FMLS V0.2S, V0.2S, V0.2S }; } @@ -418,7 +436,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x4E60CC00u, // FMLA V0.2D, V0.2D, V0.2D - 0x4EE0CC00u // FMLS V0.2D, V0.2D, V0.2D + 0x4EE0CC00u, // FMLS V0.2D, V0.2D, V0.2D }; } @@ -427,7 +445,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x5E22FC20u, // FRECPS S0, S1, S2 - 0x5EA2FC20u // FRSQRTS S0, S1, S2 + 0x5EA2FC20u, // FRSQRTS S0, S1, S2 }; } @@ -436,7 +454,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x5E62FC20u, // FRECPS D0, D1, D2 - 0x5EE2FC20u // FRSQRTS D0, D1, D2 + 0x5EE2FC20u, // FRSQRTS D0, D1, D2 }; } @@ -445,7 +463,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x0E20FC00u, // FRECPS V0.2S, V0.2S, V0.2S - 0x0EA0FC00u // FRSQRTS V0.2S, V0.2S, V0.2S + 0x0EA0FC00u, // FRSQRTS V0.2S, V0.2S, V0.2S }; } @@ -454,7 +472,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x4E60FC00u, // FRECPS V0.2D, V0.2D, V0.2D - 0x4EE0FC00u // FRSQRTS V0.2D, V0.2D, V0.2D + 0x4EE0FC00u, // FRSQRTS V0.2D, V0.2D, V0.2D }; } @@ -464,7 +482,7 @@ namespace Ryujinx.Tests.Cpu { 0x0E209400u, // MLA V0.8B, V0.8B, V0.8B 0x2E209400u, // MLS V0.8B, V0.8B, V0.8B - 0x0E209C00u // MUL V0.8B, V0.8B, V0.8B + 0x0E209C00u, // MUL V0.8B, V0.8B, V0.8B }; } @@ -474,7 +492,7 @@ namespace Ryujinx.Tests.Cpu { 0x4E209400u, // MLA V0.16B, V0.16B, V0.16B 0x6E209400u, // MLS V0.16B, V0.16B, V0.16B - 0x4E209C00u // MUL V0.16B, V0.16B, V0.16B + 0x4E209C00u, // MUL V0.16B, V0.16B, V0.16B }; } @@ -485,7 +503,7 @@ namespace Ryujinx.Tests.Cpu 0x5E000000u, // SHA1C Q0, S0, V0.4S 0x5E002000u, // SHA1M Q0, S0, V0.4S 0x5E001000u, // SHA1P Q0, S0, V0.4S - 0x5E003000u // SHA1SU0 V0.4S, V0.4S, V0.4S + 0x5E003000u, // SHA1SU0 V0.4S, V0.4S, V0.4S }; } @@ -495,7 +513,7 @@ namespace Ryujinx.Tests.Cpu { 0x5E004000u, // SHA256H Q0, Q0, V0.4S 0x5E005000u, // SHA256H2 Q0, Q0, V0.4S - 0x5E006000u // SHA256SU1 V0.4S, V0.4S, V0.4S + 0x5E006000u, // SHA256SU1 V0.4S, V0.4S, V0.4S }; } @@ -510,7 +528,7 @@ namespace Ryujinx.Tests.Cpu 0x2E206400u, // UMAX V0.8B, V0.8B, V0.8B 0x2E20A400u, // UMAXP V0.8B, V0.8B, V0.8B 0x2E206C00u, // UMIN V0.8B, V0.8B, V0.8B - 0x2E20AC00u // UMINP V0.8B, V0.8B, V0.8B + 0x2E20AC00u, // UMINP V0.8B, V0.8B, V0.8B }; } @@ -523,7 +541,7 @@ namespace Ryujinx.Tests.Cpu 0x0E20C000u, // SMULL V0.8H, V0.8B, V0.8B 0x2E208000u, // UMLAL V0.8H, V0.8B, V0.8B 0x2E20A000u, // UMLSL V0.8H, V0.8B, V0.8B - 0x2E20C000u // UMULL V0.8H, V0.8B, V0.8B + 0x2E20C000u, // UMULL V0.8H, V0.8B, V0.8B }; } @@ -536,7 +554,7 @@ namespace Ryujinx.Tests.Cpu 0x4E20C000u, // SMULL2 V0.8H, V0.16B, V0.16B 0x6E208000u, // UMLAL2 V0.8H, V0.16B, V0.16B 0x6E20A000u, // UMLSL2 V0.8H, V0.16B, V0.16B - 0x6E20C000u // UMULL2 V0.8H, V0.16B, V0.16B + 0x6E20C000u, // UMULL2 V0.8H, V0.16B, V0.16B }; } @@ -545,7 +563,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x5EE04400u, // SSHL D0, D0, D0 - 0x7EE04400u // USHL D0, D0, D0 + 0x7EE04400u, // USHL D0, D0, D0 }; } @@ -560,7 +578,7 @@ namespace Ryujinx.Tests.Cpu 0x2E205C00u, // UQRSHL V0.8B, V0.8B, V0.8B 0x2E204C00u, // UQSHL V0.8B, V0.8B, V0.8B 0x2E205400u, // URSHL V0.8B, V0.8B, V0.8B - 0x2E204400u // USHL V0.8B, V0.8B, V0.8B + 0x2E204400u, // USHL V0.8B, V0.8B, V0.8B }; } @@ -575,19 +593,19 @@ namespace Ryujinx.Tests.Cpu 0x6E205C00u, // UQRSHL V0.16B, V0.16B, V0.16B 0x6E204C00u, // UQSHL V0.16B, V0.16B, V0.16B 0x6E205400u, // URSHL V0.16B, V0.16B, V0.16B - 0x6E204400u // USHL V0.16B, V0.16B, V0.16B + 0x6E204400u, // USHL V0.16B, V0.16B, V0.16B }; } -#endregion + #endregion private const int RndCnt = 2; - private static readonly bool NoZeros = false; - private static readonly bool NoInfs = false; - private static readonly bool NoNaNs = false; + private static readonly bool _noZeros = false; + private static readonly bool _noInfs = false; + private static readonly bool _noNaNs = false; [Test, Pairwise, Description("ADD <V><d>, <V><n>, <V><m>")] - public void Add_S_D([Values(0u)] uint rd, + public void Add_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -607,7 +625,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Add_V_8B_4H_2S([Values(0u)] uint rd, + public void Add_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -629,7 +647,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Add_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Add_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -651,7 +669,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Addhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, + public void Addhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -673,7 +691,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Addhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, + public void Addhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -695,7 +713,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Addp_V_8B_4H_2S([Values(0u)] uint rd, + public void Addp_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -717,7 +735,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Addp_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Addp_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -739,7 +757,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void And_V_8B([Values(0u)] uint rd, + public void And_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -759,7 +777,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void And_V_16B([Values(0u)] uint rd, + public void And_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -779,7 +797,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bic_V_8B([Values(0u)] uint rd, + public void Bic_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -799,7 +817,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bic_V_16B([Values(0u)] uint rd, + public void Bic_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -819,7 +837,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bif_V_8B([Values(0u)] uint rd, + public void Bif_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -839,7 +857,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bif_V_16B([Values(0u)] uint rd, + public void Bif_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -859,7 +877,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bit_V_8B([Values(0u)] uint rd, + public void Bit_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -879,7 +897,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bit_V_16B([Values(0u)] uint rd, + public void Bit_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -899,7 +917,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bsl_V_8B([Values(0u)] uint rd, + public void Bsl_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -919,7 +937,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Bsl_V_16B([Values(0u)] uint rd, + public void Bsl_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -939,7 +957,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMEQ <V><d>, <V><n>, <V><m>")] - public void Cmeq_S_D([Values(0u)] uint rd, + public void Cmeq_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -959,7 +977,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmeq_V_8B_4H_2S([Values(0u)] uint rd, + public void Cmeq_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -981,7 +999,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -1003,7 +1021,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGE <V><d>, <V><n>, <V><m>")] - public void Cmge_S_D([Values(0u)] uint rd, + public void Cmge_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -1023,7 +1041,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmge_V_8B_4H_2S([Values(0u)] uint rd, + public void Cmge_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -1045,7 +1063,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -1067,7 +1085,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGT <V><d>, <V><n>, <V><m>")] - public void Cmgt_S_D([Values(0u)] uint rd, + public void Cmgt_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -1087,7 +1105,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmgt_V_8B_4H_2S([Values(0u)] uint rd, + public void Cmgt_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -1109,7 +1127,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -1131,7 +1149,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHI <V><d>, <V><n>, <V><m>")] - public void Cmhi_S_D([Values(0u)] uint rd, + public void Cmhi_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -1151,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmhi_V_8B_4H_2S([Values(0u)] uint rd, + public void Cmhi_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -1173,7 +1191,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmhi_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Cmhi_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -1195,7 +1213,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHS <V><d>, <V><n>, <V><m>")] - public void Cmhs_S_D([Values(0u)] uint rd, + public void Cmhs_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -1215,7 +1233,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmhs_V_8B_4H_2S([Values(0u)] uint rd, + public void Cmhs_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -1237,7 +1255,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmhs_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Cmhs_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -1259,7 +1277,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMTST <V><d>, <V><n>, <V><m>")] - public void Cmtst_S_D([Values(0u)] uint rd, + public void Cmtst_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -1279,7 +1297,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmtst_V_8B_4H_2S([Values(0u)] uint rd, + public void Cmtst_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -1301,7 +1319,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Cmtst_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Cmtst_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -1323,7 +1341,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Eor_V_8B([Values(0u)] uint rd, + public void Eor_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -1343,7 +1361,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Eor_V_16B([Values(0u)] uint rd, + public void Eor_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -1362,7 +1380,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Abd_Add_Div_Mul_Mulx_Nmul_Sub_S_S([ValueSource(nameof(_F_Abd_Add_Div_Mul_Mulx_Nmul_Sub_S_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong a, [ValueSource(nameof(_1S_F_))] ulong b) @@ -1382,7 +1401,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Abd_Add_Div_Mul_Mulx_Nmul_Sub_S_D([ValueSource(nameof(_F_Abd_Add_Div_Mul_Mulx_Nmul_Sub_S_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong a, [ValueSource(nameof(_1D_F_))] ulong b) @@ -1402,9 +1422,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Abd_Add_Div_Mul_Mulx_Sub_P_V_2S_4S([ValueSource(nameof(_F_Abd_Add_Div_Mul_Mulx_Sub_P_V_2S_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_2S_F_))] ulong z, @@ -1429,9 +1450,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Abd_Add_Div_Mul_Mulx_Sub_P_V_2D([ValueSource(nameof(_F_Abd_Add_Div_Mul_Mulx_Sub_P_V_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_F_))] ulong z, @@ -1454,7 +1476,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_AcCm_EqGeGt_S_S([ValueSource(nameof(_F_AcCm_EqGeGt_S_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong a, [ValueSource(nameof(_1S_F_))] ulong b) @@ -1473,7 +1496,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_AcCm_EqGeGt_S_D([ValueSource(nameof(_F_AcCm_EqGeGt_S_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong a, [ValueSource(nameof(_1D_F_))] ulong b) @@ -1492,9 +1516,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_AcCm_EqGeGt_V_2S_4S([ValueSource(nameof(_F_AcCm_EqGeGt_V_2S_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_2S_F_))] ulong z, @@ -1518,9 +1543,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_AcCm_EqGeGt_V_2D([ValueSource(nameof(_F_AcCm_EqGeGt_V_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_F_))] ulong z, @@ -1542,7 +1568,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Cmp_Cmpe_S_S([ValueSource(nameof(_F_Cmp_Cmpe_S_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong a, [ValueSource(nameof(_1S_F_))] ulong b) @@ -1560,7 +1587,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Cmp_Cmpe_S_D([ValueSource(nameof(_F_Cmp_Cmpe_S_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong a, [ValueSource(nameof(_1D_F_))] ulong b) @@ -1578,7 +1606,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Madd_Msub_Nmadd_Nmsub_S_S([ValueSource(nameof(_F_Madd_Msub_Nmadd_Nmsub_S_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong a, [ValueSource(nameof(_1S_F_))] ulong b, @@ -1600,7 +1630,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Madd_Msub_Nmadd_Nmsub_S_D([ValueSource(nameof(_F_Madd_Msub_Nmadd_Nmsub_S_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong a, [ValueSource(nameof(_1D_F_))] ulong b, @@ -1622,7 +1654,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Max_Min_Nm_S_S([ValueSource(nameof(_F_Max_Min_Nm_S_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong a, [ValueSource(nameof(_1S_F_))] ulong b) @@ -1642,7 +1675,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Max_Min_Nm_S_D([ValueSource(nameof(_F_Max_Min_Nm_S_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong a, [ValueSource(nameof(_1D_F_))] ulong b) @@ -1662,9 +1696,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Max_Min_Nm_P_V_2S_4S([ValueSource(nameof(_F_Max_Min_Nm_P_V_2S_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_2S_F_))] ulong z, @@ -1689,9 +1724,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Max_Min_Nm_P_V_2D([ValueSource(nameof(_F_Max_Min_Nm_P_V_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_F_))] ulong z, @@ -1714,9 +1750,11 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Mla_Mls_V_2S_4S([ValueSource(nameof(_F_Mla_Mls_V_2S_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_2S_F_))] ulong z, @@ -1741,9 +1779,11 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Mla_Mls_V_2D([ValueSource(nameof(_F_Mla_Mls_V_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_F_))] ulong z, @@ -1766,7 +1806,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Recps_Rsqrts_S_S([ValueSource(nameof(_F_Recps_Rsqrts_S_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong a, [ValueSource(nameof(_1S_F_))] ulong b) @@ -1786,7 +1828,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Recps_Rsqrts_S_D([ValueSource(nameof(_F_Recps_Rsqrts_S_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong a, [ValueSource(nameof(_1D_F_))] ulong b) @@ -1806,9 +1850,11 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Recps_Rsqrts_V_2S_4S([ValueSource(nameof(_F_Recps_Rsqrts_V_2S_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_2S_F_))] ulong z, @@ -1833,9 +1879,11 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Recps_Rsqrts_V_2D([ValueSource(nameof(_F_Recps_Rsqrts_V_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_F_))] ulong z, @@ -1860,7 +1908,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void Mla_Mls_Mul_V_8B_4H_2S([ValueSource(nameof(_Mla_Mls_Mul_V_8B_4H_2S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -1882,7 +1930,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void Mla_Mls_Mul_V_16B_8H_4S([ValueSource(nameof(_Mla_Mls_Mul_V_16B_8H_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -1903,7 +1951,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Orn_V_8B([Values(0u)] uint rd, + public void Orn_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -1923,7 +1971,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Orn_V_16B([Values(0u)] uint rd, + public void Orn_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -1943,7 +1991,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Orr_V_8B([Values(0u)] uint rd, + public void Orr_V_8B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -1963,7 +2011,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Orr_V_16B([Values(0u)] uint rd, + public void Orr_V_16B([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B_))] ulong z, @@ -1983,7 +2031,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("PMULL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Pmull_V([Values(0u)] uint rd, + public void Pmull_V([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B1D_))] ulong z0, @@ -1993,7 +2041,7 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_8B1D_))] ulong b0, [ValueSource(nameof(_8B1D_))] ulong b1, [Values(0b00u, 0b11u)] uint size, // Q0: <8B, 1D> => <8H, 1Q> - [Values(0b0u, 0b1u)] uint q) // Q1: <16B, 2D> => <8H, 1Q> + [Values(0b0u, 0b1u)] uint q) // Q1: <16B, 2D> => <8H, 1Q> { uint opcode = 0x0E20E000; // PMULL V0.8H, V0.8B, V0.8B opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -2010,7 +2058,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Raddhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, + public void Raddhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -2032,7 +2080,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Raddhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, + public void Raddhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -2054,7 +2102,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RSUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Rsubhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, + public void Rsubhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -2076,7 +2124,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RSUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Rsubhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, + public void Rsubhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -2098,7 +2146,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Saba_V_8B_4H_2S([Values(0u)] uint rd, + public void Saba_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2120,7 +2168,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Saba_V_16B_8H_4S([Values(0u)] uint rd, + public void Saba_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2142,7 +2190,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Sabal_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Sabal_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2164,7 +2212,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Sabal_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Sabal_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2186,7 +2234,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sabd_V_8B_4H_2S([Values(0u)] uint rd, + public void Sabd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2208,7 +2256,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sabd_V_16B_8H_4S([Values(0u)] uint rd, + public void Sabd_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2230,7 +2278,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Sabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Sabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2252,7 +2300,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Sabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Sabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2274,7 +2322,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SADDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Saddl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Saddl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2296,7 +2344,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SADDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Saddl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Saddl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2318,12 +2366,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Saddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, + public void Saddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D> { uint opcode = 0x0E201000; // SADDW V0.8H, V0.8H, V0.8B @@ -2340,12 +2388,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Saddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, + public void Saddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D> { uint opcode = 0x4E201000; // SADDW2 V0.8H, V0.8H, V0.16B @@ -2363,7 +2411,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void Sha1c_Sha1m_Sha1p_Sha1su0_V([ValueSource(nameof(_Sha1c_Sha1m_Sha1p_Sha1su0_V_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [Random(RndCnt / 2)] ulong z0, [Random(RndCnt / 2)] ulong z1, @@ -2383,7 +2431,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void Sha256h_Sha256h2_Sha256su1_V([ValueSource(nameof(_Sha256h_Sha256h2_Sha256su1_V_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [Random(RndCnt / 2)] ulong z0, [Random(RndCnt / 2)] ulong z1, @@ -2402,7 +2450,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Shadd_V_8B_4H_2S([Values(0u)] uint rd, + public void Shadd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2424,7 +2472,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Shadd_V_16B_8H_4S([Values(0u)] uint rd, + public void Shadd_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2446,7 +2494,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Shsub_V_8B_4H_2S([Values(0u)] uint rd, + public void Shsub_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2468,7 +2516,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Shsub_V_16B_8H_4S([Values(0u)] uint rd, + public void Shsub_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2491,7 +2539,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void SU_Max_Min_P_V([ValueSource(nameof(_SU_Max_Min_P_V_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2515,7 +2563,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void SU_Mlal_Mlsl_Mull_V_8B8H_4H4S_2S2D([ValueSource(nameof(_SU_Mlal_Mlsl_Mull_V_8B8H_4H4S_2S2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2537,7 +2585,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void SU_Mlal_Mlsl_Mull_V_16B8H_8H4S_4S2D([ValueSource(nameof(_SU_Mlal_Mlsl_Mull_V_16B8H_8H4S_4S2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2558,7 +2606,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")] - public void Sqadd_S_B_H_S_D([Values(0u)] uint rd, + public void Sqadd_S_B_H_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1B1H1S1D_))] ulong z, @@ -2580,7 +2628,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqadd_V_8B_4H_2S([Values(0u)] uint rd, + public void Sqadd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2602,7 +2650,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -2624,7 +2672,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQDMULH <V><d>, <V><n>, <V><m>")] - public void Sqdmulh_S_H_S([Values(0u)] uint rd, + public void Sqdmulh_S_H_S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1H1S_))] ulong z, @@ -2646,7 +2694,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqdmulh_V_4H_2S([Values(0u)] uint rd, + public void Sqdmulh_V_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S_))] ulong z, @@ -2668,7 +2716,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqdmulh_V_8H_4S([Values(0u)] uint rd, + public void Sqdmulh_V_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S_))] ulong z, @@ -2690,7 +2738,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQRDMULH <V><d>, <V><n>, <V><m>")] - public void Sqrdmulh_S_H_S([Values(0u)] uint rd, + public void Sqrdmulh_S_H_S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1H1S_))] ulong z, @@ -2712,7 +2760,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqrdmulh_V_4H_2S([Values(0u)] uint rd, + public void Sqrdmulh_V_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S_))] ulong z, @@ -2734,7 +2782,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqrdmulh_V_8H_4S([Values(0u)] uint rd, + public void Sqrdmulh_V_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S_))] ulong z, @@ -2756,7 +2804,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQSUB <V><d>, <V><n>, <V><m>")] - public void Sqsub_S_B_H_S_D([Values(0u)] uint rd, + public void Sqsub_S_B_H_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1B1H1S1D_))] ulong z, @@ -2778,7 +2826,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqsub_V_8B_4H_2S([Values(0u)] uint rd, + public void Sqsub_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2800,7 +2848,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -2822,7 +2870,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Srhadd_V_8B_4H_2S([Values(0u)] uint rd, + public void Srhadd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2844,7 +2892,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Srhadd_V_16B_8H_4S([Values(0u)] uint rd, + public void Srhadd_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2867,7 +2915,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void ShlReg_S_D([ValueSource(nameof(_ShlReg_S_D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -2887,7 +2935,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void ShlReg_V_8B_4H_2S([ValueSource(nameof(_ShlReg_V_8B_4H_2S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2909,7 +2957,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise] public void ShlReg_V_16B_8H_4S_2D([ValueSource(nameof(_ShlReg_V_16B_8H_4S_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -2930,7 +2978,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SSUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Ssubl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Ssubl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2952,7 +3000,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SSUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Ssubl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Ssubl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -2974,12 +3022,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, + public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D> { uint opcode = 0x0E203000; // SSUBW V0.8H, V0.8H, V0.8B @@ -2996,12 +3044,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Ssubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, + public void Ssubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D> { uint opcode = 0x4E203000; // SSUBW2 V0.8H, V0.8H, V0.16B @@ -3018,7 +3066,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUB <V><d>, <V><n>, <V><m>")] - public void Sub_S_D([Values(0u)] uint rd, + public void Sub_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_))] ulong z, @@ -3038,7 +3086,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sub_V_8B_4H_2S([Values(0u)] uint rd, + public void Sub_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3060,7 +3108,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Sub_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Sub_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3082,7 +3130,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Subhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, + public void Subhn_V_8H8B_4S4H_2D2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -3104,7 +3152,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")] - public void Subhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, + public void Subhn_V_8H16B_4S8H_2D4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_4H2S1D_))] ulong z, @@ -3126,7 +3174,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Trn1_V_8B_4H_2S([Values(0u)] uint rd, + public void Trn1_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3148,7 +3196,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Trn1_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Trn1_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3170,7 +3218,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Trn2_V_8B_4H_2S([Values(0u)] uint rd, + public void Trn2_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3192,7 +3240,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Trn2_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Trn2_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3214,7 +3262,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uaba_V_8B_4H_2S([Values(0u)] uint rd, + public void Uaba_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3236,7 +3284,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uaba_V_16B_8H_4S([Values(0u)] uint rd, + public void Uaba_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3258,7 +3306,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Uabal_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Uabal_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3280,7 +3328,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Uabal_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Uabal_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3302,7 +3350,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uabd_V_8B_4H_2S([Values(0u)] uint rd, + public void Uabd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3324,7 +3372,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uabd_V_16B_8H_4S([Values(0u)] uint rd, + public void Uabd_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3346,7 +3394,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Uabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Uabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3368,7 +3416,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Uabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Uabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3390,7 +3438,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UADDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Uaddl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Uaddl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3412,7 +3460,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UADDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Uaddl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Uaddl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3434,12 +3482,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Uaddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, + public void Uaddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D> { uint opcode = 0x2E201000; // UADDW V0.8H, V0.8H, V0.8B @@ -3456,12 +3504,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Uaddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, + public void Uaddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D> { uint opcode = 0x6E201000; // UADDW2 V0.8H, V0.8H, V0.16B @@ -3478,7 +3526,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uhadd_V_8B_4H_2S([Values(0u)] uint rd, + public void Uhadd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3500,7 +3548,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uhadd_V_16B_8H_4S([Values(0u)] uint rd, + public void Uhadd_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3522,7 +3570,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uhsub_V_8B_4H_2S([Values(0u)] uint rd, + public void Uhsub_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3544,7 +3592,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uhsub_V_16B_8H_4S([Values(0u)] uint rd, + public void Uhsub_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3566,7 +3614,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQADD <V><d>, <V><n>, <V><m>")] - public void Uqadd_S_B_H_S_D([Values(0u)] uint rd, + public void Uqadd_S_B_H_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1B1H1S1D_))] ulong z, @@ -3588,7 +3636,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uqadd_V_8B_4H_2S([Values(0u)] uint rd, + public void Uqadd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3610,7 +3658,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3632,7 +3680,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQSUB <V><d>, <V><n>, <V><m>")] - public void Uqsub_S_B_H_S_D([Values(0u)] uint rd, + public void Uqsub_S_B_H_S_D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1B1H1S1D_))] ulong z, @@ -3654,7 +3702,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uqsub_V_8B_4H_2S([Values(0u)] uint rd, + public void Uqsub_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3676,7 +3724,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3698,7 +3746,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Urhadd_V_8B_4H_2S([Values(0u)] uint rd, + public void Urhadd_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3720,7 +3768,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Urhadd_V_16B_8H_4S([Values(0u)] uint rd, + public void Urhadd_V_16B_8H_4S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3742,7 +3790,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("USUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Usubl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, + public void Usubl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3764,7 +3812,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("USUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] - public void Usubl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, + public void Usubl_V_16B8H_8H4S_4S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3786,12 +3834,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, + public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D> { uint opcode = 0x2E203000; // USUBW V0.8H, V0.8H, V0.8B @@ -3808,12 +3856,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")] - public void Usubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, + public void Usubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, - [ValueSource(nameof(_4H2S1D_))] [Random(RndCnt)] ulong a, - [ValueSource(nameof(_8B4H2S_))] [Random(RndCnt)] ulong b, + [ValueSource(nameof(_4H2S1D_))][Random(RndCnt)] ulong a, + [ValueSource(nameof(_8B4H2S_))][Random(RndCnt)] ulong b, [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D> { uint opcode = 0x6E203000; // USUBW2 V0.8H, V0.8H, V0.16B @@ -3830,7 +3878,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uzp1_V_8B_4H_2S([Values(0u)] uint rd, + public void Uzp1_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3852,7 +3900,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uzp1_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Uzp1_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3874,7 +3922,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uzp2_V_8B_4H_2S([Values(0u)] uint rd, + public void Uzp2_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3896,7 +3944,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Uzp2_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Uzp2_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3918,7 +3966,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Zip1_V_8B_4H_2S([Values(0u)] uint rd, + public void Zip1_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3940,7 +3988,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Zip1_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Zip1_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -3962,7 +4010,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Zip2_V_8B_4H_2S([Values(0u)] uint rd, + public void Zip2_V_8B_4H_2S([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S_))] ulong z, @@ -3984,7 +4032,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")] - public void Zip2_V_16B_8H_4S_2D([Values(0u)] uint rd, + public void Zip2_V_16B_8H_4S_2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_8B4H2S1D_))] ulong z, @@ -4006,4 +4054,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -}
\ No newline at end of file +} |