diff options
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs index fd8ec9c5..80612f1c 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs @@ -1,7 +1,6 @@ // https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf using ARMeilleure.State; - using NUnit.Framework; namespace Ryujinx.Tests.Cpu @@ -13,8 +12,8 @@ namespace Ryujinx.Tests.Cpu [Values(1u)] uint rn, [Values(0x7B5B546573745665ul)] ulong valueH, [Values(0x63746F725D53475Dul)] ulong valueL, - [Random(2)] ulong roundKeyH, - [Random(2)] ulong roundKeyL, + [Random(2)] ulong roundKeyH, + [Random(2)] ulong roundKeyL, [Values(0x8DCAB9BC035006BCul)] ulong resultH, [Values(0x8F57161E00CAFD8Dul)] ulong resultL) { @@ -22,7 +21,7 @@ namespace Ryujinx.Tests.Cpu opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); - V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH); + V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH); ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1); @@ -45,8 +44,8 @@ namespace Ryujinx.Tests.Cpu [Values(1u)] uint rn, [Values(0x7B5B546573745665ul)] ulong valueH, [Values(0x63746F725D53475Dul)] ulong valueL, - [Random(2)] ulong roundKeyH, - [Random(2)] ulong roundKeyL, + [Random(2)] ulong roundKeyH, + [Random(2)] ulong roundKeyL, [Values(0x8F92A04DFBED204Dul)] ulong resultH, [Values(0x4C39B1402192A84Cul)] ulong resultL) { @@ -54,7 +53,7 @@ namespace Ryujinx.Tests.Cpu opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); - V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH); + V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH); ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1); @@ -73,7 +72,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("AESIMC <Vd>.16B, <Vn>.16B")] - public void Aesimc_V([Values(0u)] uint rd, + public void Aesimc_V([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(0x8DCAB9DC035006BCul)] ulong valueH, [Values(0x8F57161E00CAFD8Dul)] ulong valueL, @@ -87,8 +86,8 @@ namespace Ryujinx.Tests.Cpu ExecutionContext context = SingleOpcode( opcode, - v0: rn == 0u ? v : default(V128), - v1: rn == 1u ? v : default(V128)); + v0: rn == 0u ? v : default, + v1: rn == 1u ? v : default); Assert.Multiple(() => { @@ -108,7 +107,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("AESMC <Vd>.16B, <Vn>.16B")] - public void Aesmc_V([Values(0u)] uint rd, + public void Aesmc_V([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(0x627A6F6644B109C8ul)] ulong valueH, [Values(0x2B18330A81C3B3E5ul)] ulong valueL, @@ -122,8 +121,8 @@ namespace Ryujinx.Tests.Cpu ExecutionContext context = SingleOpcode( opcode, - v0: rn == 0u ? v : default(V128), - v1: rn == 1u ? v : default(V128)); + v0: rn == 0u ? v : default, + v1: rn == 1u ? v : default); Assert.Multiple(() => { |