diff options
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestMisc.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestMisc.cs | 131 |
1 files changed, 67 insertions, 64 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs index c86d3996..aab00976 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs @@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu { #if Misc -#region "ValueSource (Types)" + #region "ValueSource (Types)" private static IEnumerable<ulong> _1S_F_() { yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue) @@ -24,19 +24,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x00000000007FFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x0000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0x00000000FF800000ul; // -Infinity yield return 0x000000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload) @@ -54,15 +54,15 @@ namespace Ryujinx.Tests.Cpu yield return (grbg << 32) | rnd2; } } -#endregion + #endregion - private const int RndCnt = 2; + private const int RndCnt = 2; - private static readonly bool NoZeros = false; - private static readonly bool NoInfs = false; - private static readonly bool NoNaNs = false; + private static readonly bool _noZeros = false; + private static readonly bool _noInfs = false; + private static readonly bool _noNaNs = false; -#region "AluImm & Csel" + #region "AluImm & Csel" [Test, Pairwise] public void Adds_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, @@ -73,10 +73,10 @@ namespace Ryujinx.Tests.Cpu 0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT, 0b1100u, 0b1101u)] uint cond) // GT, LE> { - uint opCmn = 0xB100001F; // ADDS X31, X0, #0, LSL #0 -> CMN X0, #0, LSL #0 + uint opCmn = 0xB100001F; // ADDS X31, X0, #0, LSL #0 -> CMN X0, #0, LSL #0 uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE - opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10); + opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10); opCset |= ((cond & 15) << 12); SetContext(x0: xn); @@ -98,10 +98,10 @@ namespace Ryujinx.Tests.Cpu 0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT, 0b1100u, 0b1101u)] uint cond) // GT, LE> { - uint opCmn = 0x3100001F; // ADDS W31, W0, #0, LSL #0 -> CMN W0, #0, LSL #0 + uint opCmn = 0x3100001F; // ADDS W31, W0, #0, LSL #0 -> CMN W0, #0, LSL #0 uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE - opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10); + opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10); opCset |= ((cond & 15) << 12); SetContext(x0: wn); @@ -123,10 +123,10 @@ namespace Ryujinx.Tests.Cpu 0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT, 0b1100u, 0b1101u)] uint cond) // GT, LE> { - uint opCmp = 0xF100001F; // SUBS X31, X0, #0, LSL #0 -> CMP X0, #0, LSL #0 + uint opCmp = 0xF100001F; // SUBS X31, X0, #0, LSL #0 -> CMP X0, #0, LSL #0 uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE - opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10); + opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10); opCset |= ((cond & 15) << 12); SetContext(x0: xn); @@ -148,10 +148,10 @@ namespace Ryujinx.Tests.Cpu 0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT, 0b1100u, 0b1101u)] uint cond) // GT, LE> { - uint opCmp = 0x7100001F; // SUBS W31, W0, #0, LSL #0 -> CMP W0, #0, LSL #0 + uint opCmp = 0x7100001F; // SUBS W31, W0, #0, LSL #0 -> CMP W0, #0, LSL #0 uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE - opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10); + opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10); opCset |= ((cond & 15) << 12); SetContext(x0: wn); @@ -162,10 +162,11 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } -#endregion + #endregion + // Roots. [Explicit] - [TestCase(0xFFFFFFFDu)] // Roots. + [TestCase(0xFFFFFFFDu)] [TestCase(0x00000005u)] public void Misc1(uint a) { @@ -196,25 +197,26 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetContext().GetX(0), Is.Zero); } + // 18 integer solutions. [Explicit] - [TestCase(-20f, -5f)] // 18 integer solutions. - [TestCase(-12f, -6f)] - [TestCase(-12f, 3f)] - [TestCase( -8f, -8f)] - [TestCase( -6f, -12f)] - [TestCase( -5f, -20f)] - [TestCase( -4f, 2f)] - [TestCase( -3f, 12f)] - [TestCase( -2f, 4f)] - [TestCase( 2f, -4f)] - [TestCase( 3f, -12f)] - [TestCase( 4f, -2f)] - [TestCase( 5f, 20f)] - [TestCase( 6f, 12f)] - [TestCase( 8f, 8f)] - [TestCase( 12f, -3f)] - [TestCase( 12f, 6f)] - [TestCase( 20f, 5f)] + [TestCase(-20f, -5f)] + [TestCase(-12f, -6f)] + [TestCase(-12f, 3f)] + [TestCase(-8f, -8f)] + [TestCase(-6f, -12f)] + [TestCase(-5f, -20f)] + [TestCase(-4f, 2f)] + [TestCase(-3f, 12f)] + [TestCase(-2f, 4f)] + [TestCase(2f, -4f)] + [TestCase(3f, -12f)] + [TestCase(4f, -2f)] + [TestCase(5f, 20f)] + [TestCase(6f, 12f)] + [TestCase(8f, 8f)] + [TestCase(12f, -3f)] + [TestCase(12f, 6f)] + [TestCase(20f, 5f)] public void Misc2(float a, float b) { // 1 / ((1 / a + 1 / b) ^ 2) = 16 @@ -242,25 +244,26 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetContext().GetV(0).As<float>(), Is.EqualTo(16f)); } + // 18 integer solutions. [Explicit] - [TestCase(-20d, -5d)] // 18 integer solutions. - [TestCase(-12d, -6d)] - [TestCase(-12d, 3d)] - [TestCase( -8d, -8d)] - [TestCase( -6d, -12d)] - [TestCase( -5d, -20d)] - [TestCase( -4d, 2d)] - [TestCase( -3d, 12d)] - [TestCase( -2d, 4d)] - [TestCase( 2d, -4d)] - [TestCase( 3d, -12d)] - [TestCase( 4d, -2d)] - [TestCase( 5d, 20d)] - [TestCase( 6d, 12d)] - [TestCase( 8d, 8d)] - [TestCase( 12d, -3d)] - [TestCase( 12d, 6d)] - [TestCase( 20d, 5d)] + [TestCase(-20d, -5d)] + [TestCase(-12d, -6d)] + [TestCase(-12d, 3d)] + [TestCase(-8d, -8d)] + [TestCase(-6d, -12d)] + [TestCase(-5d, -20d)] + [TestCase(-4d, 2d)] + [TestCase(-3d, 12d)] + [TestCase(-2d, 4d)] + [TestCase(2d, -4d)] + [TestCase(3d, -12d)] + [TestCase(4d, -2d)] + [TestCase(5d, 20d)] + [TestCase(6d, 12d)] + [TestCase(8d, 8d)] + [TestCase(12d, -3d)] + [TestCase(12d, 6d)] + [TestCase(20d, 5d)] public void Misc3(double a, double b) { // 1 / ((1 / a + 1 / b) ^ 2) = 16 @@ -291,7 +294,7 @@ namespace Ryujinx.Tests.Cpu [Test, Ignore("The Tester supports only one return point.")] public void MiscF([Range(0u, 92u, 1u)] uint a) { - ulong Fn(uint n) + static ulong Fn(uint n) { ulong x = 0, y = 1, z; @@ -395,9 +398,9 @@ namespace Ryujinx.Tests.Cpu } [Explicit] - [TestCase( 0ul)] - [TestCase( 1ul)] - [TestCase( 2ul)] + [TestCase(0ul)] + [TestCase(1ul)] + [TestCase(2ul)] [TestCase(42ul)] public void SanityCheck(ulong a) { @@ -439,8 +442,8 @@ namespace Ryujinx.Tests.Cpu v1: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()), v2: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()), overflow: TestContext.CurrentContext.Random.NextBool(), - carry: TestContext.CurrentContext.Random.NextBool(), - zero: TestContext.CurrentContext.Random.NextBool(), + carry: TestContext.CurrentContext.Random.NextBool(), + zero: TestContext.CurrentContext.Random.NextBool(), negative: TestContext.CurrentContext.Random.NextBool()); Opcode(0xBD400001); // LDR S1, [X0,#0] @@ -463,8 +466,8 @@ namespace Ryujinx.Tests.Cpu v0: MakeVectorE0E1(a, TestContext.CurrentContext.Random.NextULong()), v1: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()), overflow: TestContext.CurrentContext.Random.NextBool(), - carry: TestContext.CurrentContext.Random.NextBool(), - zero: TestContext.CurrentContext.Random.NextBool(), + carry: TestContext.CurrentContext.Random.NextBool(), + zero: TestContext.CurrentContext.Random.NextBool(), negative: TestContext.CurrentContext.Random.NextBool()); Opcode(0x1E202008); // FCMP S0, #0.0 |